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Separate page faults from physical memory access exceptions
[riscv-tests.git]
/
isa
/
rv64si
/
csr.S
2016-11-01
Andrew Waterman
Make sure FP stores don't write memory if mstatus.FS=0.
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2016-08-27
Andrew Waterman
Update to new breakpoint & counter spec
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2016-07-22
Howard Mao
skip user-mode trap tests in rv32mi/rv64mi-p-csr if...
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2016-07-12
Andrew Waterman
Remove instruction width assumptions to support RVC
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2016-05-01
Andrew Waterman
ERET -> xRET; new memory map
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2016-03-15
Andrew Waterman
Merge branch 'priv-1.9'
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2016-03-03
Andrew Waterman
Some S-mode tests really only belong in M-mode
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2016-03-03
Andrew Waterman
WIP on priv spec v1.9
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2015-05-09
Andrew Waterman
Update to privileged architecture version 1.7
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2015-03-25
Yunsup Lee
split out S-mode tests and M-mode tests
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2015-03-17
Andrew Waterman
Merge [shm]call into ecall, [shm]ret into eret
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2015-01-10
Andrew Waterman
Add LICENSE
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2014-02-11
Adam Izraelevitz
Merge branch 'master' of github.com:ucb-bar/riscv-tests
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2014-02-01
Andrew Waterman
Add rv32si tests, including illegality of shamt[5]
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2014-01-31
Andrew Waterman
Make CSR test much more robust
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2014-01-22
Andrew Waterman
Add CSRRx/CSRRxI test
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