git.libre-soc.org Git - riscv-isa-sim.git/history

2010-09-13	Andrew Waterman	[xcc, sim] branches now are next-PC-based, not PC-based	blob \| commitdiff \| raw
2010-09-11	Andrew Waterman	[sim, pk] cleaned up exception vectors and FP exc flags	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	Merge branch 'master' of /project/eecs/parlab/git/proje...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Andrew Waterman	[pk, sim] added interrupt support to sim; added timer...	blob \| commitdiff \| raw \| diff to current
2010-09-07	Andrew Waterman	[sim, xcc] branches now have 2-byte-aligned displacements	blob \| commitdiff \| raw \| diff to current
2010-08-18	Andrew Waterman	[sim] integrated SoftFloat-3 with ISA sim; removed...	blob \| commitdiff \| raw \| diff to current
2010-08-10	Andrew Waterman	[xcc,sim] implement FP using softfloat	blob \| commitdiff \| raw \| diff to current
2010-08-06	Andrew Waterman	[sim,xcc] Added first few Hauser FP insns (sign-injection)	blob \| commitdiff \| raw \| diff to current
2010-08-05	Andrew Waterman	[xcc,pk,sim] Added first part of FP support	blob \| commitdiff \| raw \| diff to current
2010-07-29	Andrew Waterman	[sim,xcc] Changed instruction format to RISC-V	blob \| commitdiff \| raw \| diff to current
2010-07-19	Andrew Waterman	Reorganized directory structure	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike