Update to new privileged ISA
[riscv-isa-sim.git] / riscv / decode.h
2013-11-25 Andrew WatermanUpdate to new privileged ISA
2013-11-06 Yunsup Leecorrectly trap when SR_EA is disabled
2013-09-27 Christopher CelioAdded commit logging (--enable-commitlog). Also fixed...
2013-09-27 Andrew WatermanUse WRITE_RD/WRITE_FRD macros to write registers
2013-09-21 Andrew WatermanUpdate ISA encoding and AUIPC semantics
2013-09-11 Andrew WatermanImplement zany immediates
2013-09-10 Andrew WatermanAdd rd field to JAL; drop J
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-08-08 Andrew WatermanDisentangle some header files
2013-07-27 Andrew WatermanRemove more vector stuff
2013-07-26 Andrew WatermanRip out RVC for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-04-24 Yunsup Leefixes to correctly simulate the vector unit
2013-03-26 Andrew Watermanadd BSD license
2013-03-26 Andrew Watermantruncate effective addresses in rv32
2013-03-26 Andrew Watermansupport compilation with gcc 4.7
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-03-24 Andrew Watermannew supervisor mode
2012-03-20 Andrew Watermanabstract regfile write port
2012-03-20 Andrew Watermanabstract regfile behind object
2012-01-23 Andrew Watermandisentangle decode.h from other headers
2012-01-23 Andrew Watermanwork around gcc 4.4 bug
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-14 Andrew Waterman[sim] initial support for virtual memory
2011-04-24 Andrew Waterman[xcc,sim,opcodes] added more RVC instructions
2011-04-19 Andrew Waterman[xcc,sim,opcodes] added rvc conditional branches
2011-04-17 Andrew Waterman[sim] removed undefined behavior for non-canonical...
2011-04-13 Andrew Waterman[xcc,sim] fixed RM field
2011-04-12 Andrew Waterman[xcc,sim] rvc loads and stores
2011-04-12 Andrew Waterman[sim] fixed FSR exception field bug
2011-04-12 Andrew Waterman[xcc,sim,opcodes] more rvc instructions and bug fixes
2011-04-10 Yunsup Lee[sim] add vt stuff
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-04-10 Andrew Waterman[xcc,pk,sim,opcodes] added first RVC instruction
2011-03-01 Andrew Waterman[xcc,sim] branches are pc-relative (not pc+4) again
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2011-02-02 Andrew Waterman[xcc,opcodes,pk,sim] cleanup to FP ISA
2011-02-02 Andrew Waterman[sim] added nearest/ties to max magnitude rounding...
2011-01-26 Andrew Waterman[opcodes,pk,sim,xcc] great renumbering of 2011, part...
2011-01-19 Andrew Waterman[opcodes, sim, xcc] made *w insns illegal in RV32
2011-01-04 Yunsup Lee[opcodes,pk,sim,xcc] flip fields to favor little endian
2010-12-27 Andrew Waterman[sim] cleaned up handling of link register
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] Tweaked FP encoding
2010-11-22 Andrew Waterman[xcc, sim, pk, opcodes] new instruction encoding!
2010-11-22 Andrew Waterman[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
2010-10-26 Andrew Waterman[sim,xcc,pk,opcodes] static rounding modes for FP insns
2010-10-16 Andrew Waterman[pk, sim] added FPU emulation support to proxy kernel
2010-10-12 Andrew Waterman[sim] added writeback tracing
2010-10-06 Andrew Waterman[xcc] removed CEXC field from FSR
2010-09-23 Andrew Waterman[xcc, sim] eliminated zero-extended immediates
2010-09-21 Andrew Waterman[xcc, sim] changed instruction format so imm12 subs...
2010-09-13 Andrew Waterman[xcc, sim] moved shamt field and renamed shifts
2010-09-13 Andrew Waterman[xcc, sim] branches now are next-PC-based, not PC-based
2010-09-11 Andrew Waterman[sim, pk] cleaned up exception vectors and FP exc flags
2010-09-09 Andrew WatermanMerge branch 'master' of /project/eecs/parlab/git/proje...
2010-09-09 Andrew Waterman[pk, sim] added interrupt support to sim; added timer...
2010-09-07 Andrew Waterman[sim, xcc] branches now have 2-byte-aligned displacements
2010-08-18 Andrew Waterman[sim] integrated SoftFloat-3 with ISA sim; removed...
2010-08-10 Andrew Waterman[xcc,sim] implement FP using softfloat
2010-08-06 Andrew Waterman[sim,xcc] Added first few Hauser FP insns (sign-injection)
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-29 Andrew Waterman[sim,xcc] Changed instruction format to RISC-V
2010-07-19 Andrew WatermanReorganized directory structure