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Fix store to clear debug interrupt.
[riscv-isa-sim.git]
/
riscv
/
gdbserver.h
2016-05-23
Tim Newsome
Fix store to clear debug interrupt.
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2016-05-23
Tim Newsome
Add debug_module bus device.
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2016-05-23
Tim Newsome
ROM -> RAM -> ROM, waiting for debug int.
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2016-05-23
Tim Newsome
Only halt on ebreak if a debugger is attached.
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2016-05-23
Tim Newsome
Add --gdb-port
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2016-05-23
Tim Newsome
Implement register writes.
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2016-05-23
Tim Newsome
Flush icache when using swbps and report to gdb.
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2016-05-23
Tim Newsome
Software breakpoints seem to work.
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2016-05-23
Tim Newsome
Looks like single step works.
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2016-05-23
Tim Newsome
Implement binary memory write.
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2016-05-23
Tim Newsome
Now you can halt/continue from gdb.
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2016-05-23
Tim Newsome
Register read looks sane now.
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2016-05-23
Tim Newsome
gdb can now read spike memory.
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2016-05-23
Tim Newsome
Hack to the point where gdb reads a register.
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2016-05-23
Tim Newsome
Listen on a socket for gdb to connect to.
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