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Implement timer faithfully
[riscv-isa-sim.git]
/
riscv
/
htif.cc
2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-09-23
Andrew Waterman
Fix Scott's deadlock
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2013-07-13
Andrew Waterman
Eliminate infinite loop in debug mode
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2013-03-26
Andrew Waterman
add BSD license
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2013-03-26
Andrew Waterman
ignore host writes to fromhost if old value not 0
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2013-02-13
Andrew Waterman
make HTIF interactions deterministic; fix race
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2013-01-26
Andrew Waterman
remove unnecessary #include
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2013-01-26
Andrew Waterman
change htif to link against libfesvr
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2012-08-31
Andrew Waterman
new tohost/fromhost semantics
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2012-07-23
Andrew Waterman
correct HTIF reset behavior
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2012-05-09
Andrew Waterman
per-core tohost/fromhost registers
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2012-03-24
Andrew Waterman
new supervisor mode
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2012-03-20
Andrew Waterman
abstract regfile behind object
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2012-02-20
Andrew Waterman
new HTIF protocol. update your fesvr.
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2012-02-18
Andrew Waterman
implement lighter-weight htif packet header
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2012-02-01
Andrew Waterman
poll HTIF occasionally
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2012-01-12
Andrew Waterman
fix compilation for gcc 4.6.1
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2011-10-19
Yunsup Lee
Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim
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2011-10-19
Yunsup Lee
yunsup made this fix..ask him
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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