git.libre-soc.org Git - riscv-isa-sim.git/history

2018-09-26	Luke Kenneth Casso...	ok this is tricky: an extra parameter has to be passed...	blob \| commitdiff \| raw
2018-09-26	Luke Kenneth Casso...	check if register redirection is active, and if vectori...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	comment why sv_insn_t is set up the way it is; add...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	shuffle things around a bit for sv, put rv32/64_name...	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike