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Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git]
/
riscv
/
insns
/
amomin_w.h
2016-11-10
Andrew Waterman
AMOs should always return store faults, not load faults
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2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-01-21
Andrew Waterman
[sim, pk, xcc, opcodes] great instruction renaming...
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