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Fix implementation of FMIN/FMAX NaN case
[riscv-isa-sim.git] / riscv / insns / amoxor_d.h
2016-11-10 Andrew WatermanAMOs should always return store faults, not load faults blob | commitdiff | raw
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag blob | commitdiff | raw | diff to current
2015-03-13 Andrew WatermanUpdate to new privileged spec blob | commitdiff | raw | diff to current
2013-09-27 Andrew WatermanUse WRITE_RD/WRITE_FRD macros to write registers blob | commitdiff | raw | diff to current
2013-09-11 Andrew WatermanAdd AMOXOR blob | commitdiff | raw | diff to current
Simple-V augmented version of spike