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Merge pull request #113 from riscv/debug_readme
[riscv-isa-sim.git]
/
riscv
/
insns
/
divuw.h
2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2012-02-16
Andrew Waterman
reimplement div[u][w]/rem[u][w]
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2012-01-30
Yunsup Lee
fix divide by zero bugs
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-04-17
Andrew Waterman
[sim] removed undefined behavior for non-canonical...
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2011-01-19
Andrew Waterman
[opcodes, sim, xcc] made *w insns illegal in RV32
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2010-11-22
Andrew Waterman
[sim] handle integer division overflow
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2010-11-22
Andrew Waterman
[xcc, sim, pk, opcodes] new instruction encoding!
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2010-09-21
Andrew Waterman
[xcc, sim] changed instruction format so imm12 subs...
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2010-08-04
Andrew Waterman
[pk,sim,xcc] Renamed instructions to RISC-V spec
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