Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git] / riscv / insns / jalr.h
2015-01-03 Andrew WatermanOn misaligned fetch, set EPC to target, not branch...
2013-09-27 Andrew WatermanUse WRITE_RD/WRITE_FRD macros to write registers
2013-09-11 Andrew WatermanImplement zany immediates
2013-08-08 Andrew WatermanIgnore JALR's effective address LSB
2013-07-25 Andrew WatermanRemove JALR static hints
2010-07-29 Andrew Waterman[gcc] generate code for complex branches
2010-07-19 Andrew WatermanReorganized directory structure