Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git] / riscv / insns / mret.h
2017-05-17 Palmer DabbeltMerge remote-tracking branch 'origin/priv-1.10'
2017-04-17 Megan WachsMerge remote-tracking branch 'origin/priv-1.10' into...
2017-03-16 Andrew WatermanSimplify interrupt-stack discipline
2017-02-07 Tim NewsomeMerge pull request #83 from bacam/gdb-protocol-fixes
2017-02-02 Andrew WatermanSet xPIE=1 on xRET
2016-04-20 Andrew WatermanSplit ERET into URET, SRET, HRET, MRET
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-13 Andrew WatermanUpdate to new privileged spec