2011-11-11 |
Andrew Waterman | Changed supervisor mode |
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2011-06-20 |
Andrew Waterman | temporary undoing of renaming |
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2011-06-13 |
Andrew Waterman | [sim] renamed to riscv-isa-run |
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2011-05-29 |
Andrew Waterman | [fesvr,xcc,sim] fixed multicore sim for akaros |
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2011-05-18 |
Yunsup Lee | [opcodes,pk,sim] add more vector traps (for #banks... |
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2011-05-16 |
Andrew Waterman | [sim,pk] cleanups & initial virtual memory support |
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2011-02-05 |
Andrew Waterman | [sim,pk] added interrupt-pending field to cause reg |
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2010-10-05 |
Andrew Waterman | [xcc,sim] eliminated vectored traps |
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2010-09-21 |
Andrew Waterman | [xcc, sim] changed instruction format so imm12 subs... |
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2010-09-09 |
Andrew Waterman | Merge branch 'master' of /project/eecs/parlab/git/proje... |
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2010-09-09 |
Andrew Waterman | [pk, sim] added interrupt support to sim; added timer... |
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2010-09-08 |
Yunsup Lee | [sim] add while to interactive_until |
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2010-09-07 |
Andrew Waterman | [sim, xcc] added PCRs to replace k0 and k1 |
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2010-08-24 |
Andrew Waterman | [sim] privileged mode support for 32-bit operation |
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2010-08-04 |
Andrew Waterman | [pk,sim,xcc] Renamed instructions to RISC-V spec |
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