projects / riscv-isa-sim.git / history
| 2015-04-02 | Andrew Waterman | Simplify RV32 comparisons | blob | commitdiff | raw |
| 2013-09-27 | Andrew Waterman | Use WRITE_RD/WRITE_FRD macros to write registers | blob | commitdiff | raw | diff to current |
| 2011-06-20 | Andrew Waterman | temporary undoing of renaming | blob | commitdiff | raw | diff to current |
| 2011-06-13 | Andrew Waterman | [sim] renamed to riscv-isa-run | blob | commitdiff | raw |
| 2010-11-22 | Andrew Waterman | [xcc, sim, pk, opcodes] new instruction encoding! | blob | commitdiff | raw | diff to current |
| 2010-09-21 | Andrew Waterman | [xcc, sim] changed instruction format so imm12 subs... | blob | commitdiff | raw | diff to current |
| 2010-07-29 | Andrew Waterman | [sim,xcc] Changed instruction format to RISC-V | blob | commitdiff | raw | diff to current |
| 2010-07-19 | Andrew Waterman | Reorganized directory structure | blob | commitdiff | raw | diff to current |