projects
/
riscv-isa-sim.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
Simplify RV32 comparisons
[riscv-isa-sim.git]
/
riscv
/
insns
/
sltiu.h
2015-04-02
Andrew Waterman
Simplify RV32 comparisons
blob
|
commitdiff
|
raw
2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
blob
|
commitdiff
|
raw
|
diff to current
2013-09-11
Andrew Waterman
Implement zany immediates
blob
|
commitdiff
|
raw
|
diff to current
2011-06-20
Andrew Waterman
temporary undoing of renaming
blob
|
commitdiff
|
raw
|
diff to current
2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
blob
|
commitdiff
|
raw
2010-11-22
Andrew Waterman
[xcc, sim, pk, opcodes] new instruction encoding!
blob
|
commitdiff
|
raw
|
diff to current
2010-09-21
Andrew Waterman
[xcc, sim] changed instruction format so imm12 subs...
blob
|
commitdiff
|
raw
|
diff to current
2010-09-10
Andrew Waterman
Revert "[xcc, sim] added slei/sleui in lieu of slti...
blob
|
commitdiff
|
raw
|
diff to current
2010-09-07
Andrew Waterman
[xcc, sim] added slei/sleui in lieu of slti/sltiu
blob
|
commitdiff
|
raw
2010-07-29
Andrew Waterman
[sim,xcc] Changed instruction format to RISC-V
blob
|
commitdiff
|
raw
|
diff to current
2010-07-19
Andrew Waterman
Reorganized directory structure
blob
|
commitdiff
|
raw
|
diff to current