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fix slli/slliw encoding bug
[riscv-isa-sim.git]
/
riscv
/
opcodes.h
2013-11-21
Yunsup Lee
fix slli/slliw encoding bug
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2013-09-21
Andrew Waterman
Update ISA encoding and AUIPC semantics
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2013-09-15
Andrew Waterman
ISA changes
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2013-09-11
Andrew Waterman
Add AMOXOR
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2013-09-11
Andrew Waterman
Implement zany immediates
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2013-09-10
Andrew Waterman
Add rd field to JAL; drop J
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2013-08-08
Andrew Waterman
Rename MTFSR/MFFSR to FSSR/FRSR
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2013-08-08
Andrew Waterman
Swap J and JALR encoding
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2013-07-27
Andrew Waterman
New supervisor mode
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2013-07-27
Andrew Waterman
Rename MFTX/MXTF to FMV
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2013-07-26
Andrew Waterman
Rip out Hwacha for now
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2013-07-26
Andrew Waterman
Rip out RVC for now
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2013-07-25
Andrew Waterman
Remove JALR static hints
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2013-04-17
Andrew Waterman
add AUIPC insn; remove RDNPC insn
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2013-03-30
Andrew Waterman
add load-reserved/store-conditional instructions
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2013-03-27
Andrew Waterman
opcodes.h must only contain DECLARE_INSN() lines
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2013-03-26
Andrew Waterman
add BSD license
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2012-03-24
Andrew Waterman
new supervisor mode
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2012-03-19
Andrew Waterman
update vector fences
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2012-03-18
Yunsup Lee
clean up vector exception instructions
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2012-03-14
Yunsup Lee
add more instructions for vector exception handling
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2012-03-14
Yunsup Lee
add vvcfg,vtcfg
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2012-03-13
Yunsup Lee
opcodes cleanup
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2012-03-10
Yunsup Lee
slight change to vector supervisor instructions
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2012-03-03
Yunsup Lee
new instructions to handle vector exceptions
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2011-11-11
Andrew Waterman
Changed MFTX to use rs1 for its source
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-06-11
Andrew Waterman
[sim, opcodes] made sim more decoupled from opcodes
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