2017-03-21 |
Wesley W. Terpstra | riscv: remove dependency on num_cores |
blob | commitdiff | raw |
2017-03-20 |
Andrew Waterman | PUM -> SUM; expose MXR to S-mode |
blob | commitdiff | raw | diff to current |
2017-03-16 |
Andrew Waterman | Simplify interrupt-stack discipline |
blob | commitdiff | raw | diff to current |
2017-03-13 |
Andrew Waterman | Implement mstatus.TW, mstatus.TVM, and mstatus.TSR |
blob | commitdiff | raw | diff to current |
2017-02-27 |
Andrew Waterman | Sv57 and Sv64 are not spec'd yet |
blob | commitdiff | raw | diff to current |
2017-02-25 |
Andrew Waterman | New counter enable scheme |
blob | commitdiff | raw | diff to current |
2017-02-21 |
Andrew Waterman | Take M-mode interrupts over S-mode interrupts |
blob | commitdiff | raw | diff to current |
2017-02-21 |
Andrew Waterman | permit MMIO loads to MSIP bit |
blob | commitdiff | raw | diff to current |
2017-02-18 |
Andrew Waterman | Spike uarch needs TLB flush after SPTBR write |
blob | commitdiff | raw | diff to current |
2017-02-08 |
Andrew Waterman | Encode VM type in sptbr, not mstatus |
blob | commitdiff | raw | diff to current |
2017-02-07 |
Tim Newsome | Merge pull request #83 from bacam/gdb-protocol-fixes |
blob | commitdiff | raw | diff to current |
2017-02-03 |
Andrew Waterman | Fix interrupt delegation for coprocessors |
blob | commitdiff | raw | diff to current |
2017-01-08 |
Andrew Waterman | Only allow SIP.SSIP to be toggled if the interrupt... |
blob | commitdiff | raw | diff to current |
2017-01-08 |
Andrew Waterman | Make SIP.STIP read-only |
blob | commitdiff | raw | diff to current |
2016-10-10 |
Andrew Waterman | Don't force load trigger timing to After |
blob | commitdiff | raw | diff to current |
2016-09-29 |
Tim Newsome | Update trigger behavior. (#70) |
blob | commitdiff | raw | diff to current |
2016-09-10 |
Andrew Waterman | allow MAFDC bits in MISA to be modified |
blob | commitdiff | raw | diff to current |
2016-09-02 |
Andrew Waterman | Merge pull request #62 from riscv/trigger |
blob | commitdiff | raw | diff to current |
2016-09-02 |
Tim Newsome | Merge branch 'master' into trigger |
blob | commitdiff | raw | diff to current |
2016-09-01 |
Tim Newsome | Theoretically support trigger timing. |
blob | commitdiff | raw | diff to current |
2016-08-31 |
Tim Newsome | Rename tdata[0-2] to tdata[1-3]. |
blob | commitdiff | raw | diff to current |
2016-08-29 |
Tim Newsome | Rename tdata0--tdata2 to tdata1--tdata3. |
blob | commitdiff | raw | diff to current |
2016-08-27 |
Andrew Waterman | Add (degenerate) performance counter facility |
blob | commitdiff | raw | diff to current |
2016-08-26 |
Andrew Waterman | Allow reads from tdrdata registers |
blob | commitdiff | raw | diff to current |
2016-08-26 |
Andrew Waterman | partially update spike to newer debug spec |
blob | commitdiff | raw | diff to current |
2016-08-26 |
Andrew Waterman | Fix spike interactive (-d) mode |
blob | commitdiff | raw | diff to current |
2016-08-23 |
Andrew Waterman | remove HWBPCOUNT field of DCSR |
blob | commitdiff | raw | diff to current |
2016-08-22 |
Tim Newsome | Implement address and data triggers. |
blob | commitdiff | raw | diff to current |
2016-08-17 |
Andrew Waterman | Allow mstatus.MPP to store bad values; instead, validat... |
blob | commitdiff | raw | diff to current |
2016-07-28 |
Tim Newsome | Add support for virtual priv register. (#59) |
blob | commitdiff | raw | diff to current |
2016-07-22 |
Andrew Waterman | Set U bit in misa register |
blob | commitdiff | raw | diff to current |
2016-07-12 |
Andrew Waterman | Don't treat RVC NOP as illegal instruction |
blob | commitdiff | raw | diff to current |
2016-07-06 |
Andrew Waterman | Update to new PTE format |
blob | commitdiff | raw | diff to current |
2016-06-29 |
Andrew Waterman | Disassemble RVC instructions based on XLEN |
blob | commitdiff | raw | diff to current |
2016-06-23 |
Andrew Waterman | Remove legacy HTIF; implement HTIF directly |
blob | commitdiff | raw | diff to current |
2016-06-23 |
Andrew Waterman | Fix paddr_bits computation prior to VM setup |
blob | commitdiff | raw | diff to current |
2016-06-18 |
Andrew Waterman | Merge sasid into sptbr |
blob | commitdiff | raw | diff to current |
2016-06-09 |
Andrew Waterman | Trap on tdrdata registers when tdrselect[XLEN-1]=0 |
blob | commitdiff | raw | diff to current |
2016-06-09 |
Andrew Waterman | Add degenerate HW breakpoint implementation |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Turn off debugging. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Tell gdb we can handle large packets. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Exceptions in Debug Mode don't update any regs. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Remove already-implemented TODO. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Implement ebreak[mhsu]. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Remove dependency on include file in my homedir. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Make -H halt the core right out of reset. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Halt when gdb user hits ^C. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Single step appears to work. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Fix off-by-two in general read registers. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Remove unused code. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Add dret. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Implement single memory read access. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Exceptions in Debug Mode, stay in Debug Mode. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Continue works well enough for DebugTest.test_exit |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Refactor how we track in-progress operations. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | processor_t unfriends gdbserver_t. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Add debug_module bus device. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Can jump to and execute Debug ROM. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | When gdb connects, jump to Debug ROM and segfault. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Gutting direct-access gdb. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Add writing to DCSR, DPC, DSCRATCH. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Only halt on ebreak if a debugger is attached. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Flush icache when using swbps and report to gdb. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Software breakpoints seem to work. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Looks like single step works. |
blob | commitdiff | raw | diff to current |
2016-05-23 |
Tim Newsome | Now you can halt/continue from gdb. |
blob | commitdiff | raw | diff to current |
2016-05-22 |
Andrew Waterman | Allow delegation of device interrupts |
blob | commitdiff | raw | diff to current |
2016-05-02 |
Andrew Waterman | Add back IPI support |
blob | commitdiff | raw | diff to current |
2016-05-02 |
Andrew Waterman | Remove MIPI; mip.MSIP bit is read-only |
blob | commitdiff | raw | diff to current |
2016-05-02 |
Andrew Waterman | Remove tohost/fromhost registers |
blob | commitdiff | raw | diff to current |
2016-05-01 |
Andrew Waterman | Initialize mtvec to DEFAULT_MTVEC |
blob | commitdiff | raw | diff to current |
2016-05-01 |
Andrew Waterman | Remove SCRs; add padding after config string |
blob | commitdiff | raw | diff to current |
2016-04-29 |
Andrew Waterman | Move much closer to new platform-M memory map |
blob | commitdiff | raw | diff to current |
2016-04-28 |
Andrew Waterman | Remove MTIME[CMP]; add RTC device |
blob | commitdiff | raw | diff to current |
2016-04-06 |
Andrew Waterman | Remove non-standard uarch CSRs |
blob | commitdiff | raw | diff to current |
2016-03-17 |
Andrew Waterman | Update definition of base field in misa register |
blob | commitdiff | raw | diff to current |
2016-03-04 |
Andrew Waterman | Fix up interrupt delegation |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | Add counter-enable registers |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | New definitions of misa/marchid/mvendorid |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | implement PUM functionality |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | sptbr now a holds a PPN, not an address |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | Use simpler MTVEC scheme |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | Zero-extend all CSR writes |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | Fix ERET serialization strategy |
blob | commitdiff | raw | diff to current |
2016-03-02 |
Andrew Waterman | WIP on priv spec v1.9 |
blob | commitdiff | raw | diff to current |
2016-01-13 |
Andrew Waterman | don't ignore data value when writing MIPI |
blob | commitdiff | raw | diff to current |
2015-11-13 |
Andrew Waterman | Generate device tree for target machine |
blob | commitdiff | raw | diff to current |
2015-10-26 |
Andrew Waterman | Fix histogram for RVC |
blob | commitdiff | raw | diff to current |
2015-09-11 |
Andrew Waterman | Simplify register_base_instructions |
blob | commitdiff | raw | diff to current |
2015-09-11 |
Andrew Waterman | Initialize mstatus.prv1/prv2 to U, not S |
blob | commitdiff | raw | diff to current |
2015-09-11 |
Andrew Waterman | Support 'G' in ISA strings |
blob | commitdiff | raw | diff to current |
2015-09-09 |
Andrew Waterman | Improve instruction fetch |
blob | commitdiff | raw | diff to current |
2015-07-30 |
Christopher Celio | Added error message when trying to use histogram |
blob | commitdiff | raw | diff to current |
2015-07-05 |
Andrew Waterman | New machine-mode timer facility |
blob | commitdiff | raw | diff to current |
2015-06-01 |
Andrew Waterman | Use single, shared real-time counter |
blob | commitdiff | raw | diff to current |
2015-06-01 |
Andrew Waterman | Execute exactly the # of insns passed to step() |
blob | commitdiff | raw | diff to current |
2015-06-01 |
Andrew Waterman | Fix performance bug when CSR accesses are common |
blob | commitdiff | raw | diff to current |
2015-06-01 |
Andrew Waterman | Take interrupts as soon as interrupts are enabled |
blob | commitdiff | raw | diff to current |
2015-05-09 |
Andrew Waterman | Upgrade to privileged architecture 1.7 |
blob | commitdiff | raw | diff to current |
next |