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htif: catch proper store exception (#44)
[riscv-isa-sim.git]
/
riscv
/
riscv.mk.in
2016-05-19
Tim Newsome
Merge pull request #42 from csail-csg/master
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2016-05-19
acw1251
Removed devicetree.h from riscv.mk.in since it no longe...
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2016-05-18
acw1251
Added missing header files to riscv.mk.in
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2016-04-28
Andrew Waterman
Remove MTIME[CMP]; add RTC device
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2016-04-20
Andrew Waterman
Split ERET into URET, SRET, HRET, MRET
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2015-11-13
Andrew Waterman
Generate device tree for target machine
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2015-10-20
Andrew Waterman
Update to hopefully final RVC 1.9 encoding
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2015-10-06
Andrew Waterman
more work towards RVC 1.8
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2015-10-02
Andrew Waterman
work towards rvc 1.8
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2015-09-11
Andrew Waterman
Merge pull request #32 from riscv/insn-list
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2015-09-11
Albert Ou
Fix non-portable sed commands generating insn_list.h
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2015-09-09
Andrew Waterman
Improve instruction fetch
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2015-05-15
Andrew Waterman
Merge pull request #20 from palmer-dabbelt/package
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2015-05-13
Palmer Dabbelt
Install "disasm.h"
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2015-04-04
Andrew Waterman
Support setting ISA/subsets with --isa flag
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2015-01-02
Andrew Waterman
Reduce dependences on auto-generated code
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2014-11-25
Andrew Waterman
Factor out the dummy RoCC accelerator
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2014-11-20
Andrew Waterman
Add missing makefile dependence
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2014-09-27
Andrew Waterman
Avoid some unused variable warnings
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2014-09-27
Andrew Waterman
Avoid use of __int128_t
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2014-07-07
Andrew Waterman
Use precompiled headers to speed up compilation
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2014-01-27
Andrew Waterman
Eliminate hwacha <-> riscv circular dependence
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2014-01-26
Andrew Waterman
Merge softfloat_riscv into softfloat
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2014-01-14
Andrew Waterman
Improve performance for branchy code
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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2013-09-15
Andrew Waterman
Add helper disassembly program
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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2013-07-26
Andrew Waterman
Generate instruction decoder dynamically
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2013-07-22
Andrew Waterman
Add xspike program
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2013-06-03
Andrew Waterman
use coreutils `seq' instead of hacky `range'
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2013-05-15
Yunsup Lee
fix make issue
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2013-05-14
Yunsup Lee
change riscv-isa-run to spike
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2013-05-06
Andrew Waterman
make Makefile sh-friendly
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2013-04-25
Andrew Waterman
fix(?) circular dependence on generated headers
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2013-04-22
Andrew Waterman
correctly depend on dispatch.h
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2013-04-20
Andrew Waterman
remove circular dependence in Makefile
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2013-04-17
Andrew Waterman
add AUIPC insn; remove RDNPC insn
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2013-02-13
Andrew Waterman
add I$/D$/L2$ simulators
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2011-11-12
Your Name
Remove dependence on binutils
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-06-12
Andrew Waterman
[xcc] fixed simulator build time
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2011-06-11
Andrew Waterman
[sim, opcodes] made sim more decoupled from opcodes
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2011-05-29
Andrew Waterman
[sim,opcodes] improved sim build and run performance
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2011-05-16
Andrew Waterman
[sim,pk] cleanups & initial virtual memory support
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2011-04-15
Andrew Waterman
[sim] added icache simulator (disabled by default)
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2010-08-18
Andrew Waterman
[sim] integrated SoftFloat-3 with ISA sim; removed...
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2010-08-10
Andrew Waterman
[xcc,sim] implement FP using softfloat
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2010-08-10
Andrew Waterman
[sim] removed unused elf loader
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2010-07-22
Andrew Waterman
[pk,sim] first cut of appserver communication link
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2010-07-19
Andrew Waterman
Reorganized directory structure
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