git.libre-soc.org Git - riscv-isa-sim.git/history

2018-09-27	Luke Kenneth Casso...	add sv predication function	blob \| commitdiff \| raw
2018-09-26	Luke Kenneth Casso...	cache the sv redirected register values on each loop	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	remembered that the use of sv registers have to be...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	ok this is tricky: an extra parameter has to be passed...	blob \| commitdiff \| raw \| diff to current
2018-09-26	Luke Kenneth Casso...	move sv remap function to sv.cc (not inline)	blob \| commitdiff \| raw \| diff to current
2018-09-25	Luke Kenneth Casso...	rename sv vlen to sv voffs, add csr and reg tables	blob \| commitdiff \| raw \| diff to current
2018-09-25	Luke Kenneth Casso...	add reference to vector length in sv	blob \| commitdiff \| raw \| diff to current
2018-09-25	Luke Kenneth Casso...	use sv_insn_t class in instruction template	blob \| commitdiff \| raw \| diff to current
2018-09-25	Luke Kenneth Casso...	add sv_insn_t class (inherits from insn_t)	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike