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Fix writing odd numbers of bytes to odd addresses.
[riscv-isa-sim.git]
/
spike_main
/
disasm.cc
2016-04-28
Andrew Waterman
Remove MTIME[CMP]; add RTC device
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2016-04-20
Andrew Waterman
Split ERET into URET, SRET, HRET, MRET
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2015-10-20
Andrew Waterman
Update to hopefully final RVC 1.9 encoding
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2015-10-06
Andrew Waterman
more work towards RVC 1.8
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2015-10-02
Andrew Waterman
work towards rvc 1.8
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2015-09-04
Andrew Waterman
Move towards RVC v1.8
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2015-06-01
Andrew Waterman
New RV64C proposal
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2015-03-31
Andrew Waterman
Implement RVC draft
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2015-01-05
Andrew Waterman
canonicalize assembler pseudo-ops
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2015-01-05
Andrew Waterman
Disassemble jalr x0, x1, 0 as ret
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2014-12-20
Andrew Waterman
Support building from within root directory
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