| 2020-07-31 |
Jordi Vaquero | arch-arm: Implementing SecureEL2 feature for Armv8 |
blob | commitdiff | raw |
| 2020-07-27 |
Jordi Vaquero | arch-arm: Implement ARM8.1-VHE feature |
blob | commitdiff | raw | diff to current |
| 2020-07-04 |
Bobby R. Bruce | misc: Merged m5ops_base hotfix into develop |
blob | commitdiff | raw | diff to current |
| 2020-06-22 |
Jordi Vaquero | arch-arm: Implementation of Hardware Breakpoint exception |
blob | commitdiff | raw | diff to current |
| 2020-06-12 |
Gabe Black | arch,cpu: Add a setThreadContext method to the ISA... |
blob | commitdiff | raw | diff to current |
| 2020-04-30 |
Nikos Nikoleris | arch-arm, mem-ruby, sim: Add missing overrides |
blob | commitdiff | raw | diff to current |
| 2020-04-15 |
Giacomo Travaglini | arch-arm: Override ISA::takeOverFrom for the Arm ISA |
blob | commitdiff | raw | diff to current |
| 2020-04-15 |
Giacomo Travaglini | arch-arm: Remove unnecessary haveGICv3CPUInterface |
blob | commitdiff | raw | diff to current |
| 2020-02-26 |
Bobby R. Bruce | misc: merge branch 'release-staging-v19.0.0.0' into... |
blob | commitdiff | raw | diff to current |
| 2020-02-24 |
Bobby R. Bruce | misc: Merged release-staging-v19.0.0.0 into develop |
blob | commitdiff | raw | diff to current |
| 2020-02-19 |
Adrian Herrera | arch-arm: ArmISA::clear, inval TLB cached miscregs |
blob | commitdiff | raw | diff to current |
| 2020-02-19 |
Adrian Herrera | misc: pass ThreadContext on ISA clear |
blob | commitdiff | raw | diff to current |
| 2020-02-19 |
Giacomo Travaglini | arch, arch-arm: Use BaseISA in RenameMode interface |
blob | commitdiff | raw | diff to current |
| 2020-02-18 |
Gabe Black | arm: Delete authors lists from the arm files. |
blob | commitdiff | raw | diff to current |
| 2020-02-13 |
Gabe Black | arm: "Correct" the spelling of flavor. |
blob | commitdiff | raw | diff to current |
| 2020-02-05 |
Gabe Black | arch: Introduce a base class for ISA classes. |
blob | commitdiff | raw | diff to current |
| 2020-02-04 |
Adrian Herrera | arch-arm: AArch64 reg access HCR_EL2.E2H filter |
blob | commitdiff | raw | diff to current |
| 2020-02-04 |
Adrian Herrera | arch-arm: reg access permissions highest EL helper |
blob | commitdiff | raw | diff to current |
| 2019-11-25 |
Gabe Black | arm: Stop serializing ISA values wihch are cached from... |
blob | commitdiff | raw | diff to current |
| 2019-09-06 |
Giacomo Travaglini | arch-arm: Add explicit AArch64 MiscReg banking |
blob | commitdiff | raw | diff to current |
| 2019-08-07 |
Jordi Vaquero | arch-arm: adding register control flags enabling LSE... |
blob | commitdiff | raw | diff to current |
| 2019-08-05 |
Giacomo Travaglini | arch-arm: Implement ARMv8.1-PAN, Privileged access... |
blob | commitdiff | raw | diff to current |
| 2019-05-23 |
Giacomo Travaglini | arch-arm: Expose haveGicv3CPUInterface to the ISA interface |
blob | commitdiff | raw | diff to current |
| 2019-03-14 |
Giacomo Gabrielli | arch-arm,cpu: Add initial support for Arm SVE |
blob | commitdiff | raw | diff to current |
| 2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
blob | commitdiff | raw | diff to current |
| 2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
blob | commitdiff | raw | diff to current |
| 2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
blob | commitdiff | raw | diff to current |
| 2019-01-22 |
Gabe Black | arm: Get rid of some register type definitions. |
blob | commitdiff | raw | diff to current |
| 2019-01-15 |
Giacomo Travaglini | arch-arm: Fix usage of RegId constructor for VecElem |
blob | commitdiff | raw | diff to current |
| 2019-01-10 |
Jairo Balart | dev-arm: Add a GICv3 model |
blob | commitdiff | raw | diff to current |
| 2018-11-07 |
Giacomo Travaglini | arch-arm: Implement AArch32 RVBAR |
blob | commitdiff | raw | diff to current |
| 2018-11-07 |
Giacomo Travaglini | arch-arm: Refactor ISA::clear by adding a ISA::clear32... |
blob | commitdiff | raw | diff to current |
| 2018-10-09 |
Giacomo Travaglini | arch-arm: Add have_crypto System parameter |
blob | commitdiff | raw | diff to current |
| 2018-10-01 |
Giacomo Travaglini | arch-arm: Init AArch64 ID registers in SE mode |
blob | commitdiff | raw | diff to current |
| 2018-09-13 |
Earl Ou | Fix SConstruct for asan build |
blob | commitdiff | raw | diff to current |
| 2018-09-10 |
Andreas Sandberg | arm: Add support for tracking TCs in ISA devices |
blob | commitdiff | raw | diff to current |
| 2018-05-29 |
Giacomo Travaglini | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL... |
blob | commitdiff | raw | diff to current |
| 2018-04-18 |
Giacomo Travaglini | arch-arm: Adding MiscReg Priv (EL1) global flag |
blob | commitdiff | raw | diff to current |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Distinguish IS TLBI from non-IS |
blob | commitdiff | raw | diff to current |
| 2018-03-23 |
Giacomo Travaglini | arch-arm: Created function for TLB ASID Invalidation |
blob | commitdiff | raw | diff to current |
| 2018-03-12 |
Giacomo Travaglini | arch-arm: Adding IPA-Based Invalidating instructions |
blob | commitdiff | raw | diff to current |
| 2018-02-16 |
Giacomo Travaglini | arch-arm: Arch regs and pseudo regs distinction |
blob | commitdiff | raw | diff to current |
| 2018-01-29 |
Curtis Dunham | arch-arm: understandably initialize register permissions |
blob | commitdiff | raw | diff to current |
| 2018-01-29 |
Curtis Dunham | arm: extend MiscReg metadata structures |
blob | commitdiff | raw | diff to current |
| 2018-01-29 |
Curtis Dunham | arch-arm: understandably initialize register mappings |
blob | commitdiff | raw | diff to current |
| 2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Added interface for vector reg file |
blob | commitdiff | raw | diff to current |
| 2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Simplify the rename interface and use RegId |
blob | commitdiff | raw | diff to current |
| 2016-12-19 |
Curtis Dunham | arm: miscreg refactoring |
blob | commitdiff | raw | diff to current |
| 2016-12-19 |
Curtis Dunham | arm: update AArch{64,32} register mappings |
blob | commitdiff | raw | diff to current |
| 2016-08-02 |
Curtis Dunham | arm: enable EL2 support |
blob | commitdiff | raw | diff to current |
| 2015-10-09 |
Rekai Gonzalez Alb... | isa: Add parameter to pick different decoder inside ISA |
blob | commitdiff | raw | diff to current |
| 2015-07-28 |
Nilay Vaish | revert 5af8f40d8f2c |
blob | commitdiff | raw | diff to current |
| 2015-07-26 |
Nilay Vaish | cpu: implements vector registers |
blob | commitdiff | raw | diff to current |
| 2015-07-07 |
Andreas Sandberg | sim: Refactor the serialization base class |
blob | commitdiff | raw | diff to current |
| 2015-05-23 |
Andreas Sandberg | dev, arm: Refactor and clean up the generic timer model |
blob | commitdiff | raw | diff to current |
| 2015-05-05 |
Andreas Hansson | arm: Remove unnecessary boot uncachability |
blob | commitdiff | raw | diff to current |
| 2015-03-02 |
Andreas Sandberg | arm: Don't truncate 16-bit ASIDs to 8 bits |
blob | commitdiff | raw | diff to current |
| 2014-10-30 |
Ali Saidi | automated merge |
blob | commitdiff | raw | diff to current |
| 2014-10-30 |
Ali Saidi | arm: Fix multi-system AArch64 boot w/caches. |
blob | commitdiff | raw | diff to current |
| 2014-10-16 |
Andreas Sandberg | arm: Add a model of an ARM PMUv3 |
blob | commitdiff | raw | diff to current |
| 2014-04-29 |
Curtis Dunham | arm: use condition code registers for ARM ISA |
blob | commitdiff | raw | diff to current |
| 2014-01-24 |
ARM gem5 Developers | arm: Add support for ARMv8 (AArch64 & AArch32) |
blob | commitdiff | raw | diff to current |
| 2014-01-24 |
Andreas Hansson | arch: Make all register index flattening const |
blob | commitdiff | raw | diff to current |
| 2013-10-15 |
Yasuko Eckert | cpu: add a condition-code register class |
blob | commitdiff | raw | diff to current |
| 2013-02-19 |
Andreas Hansson | scons: Add warning for overloaded virtual functions |
blob | commitdiff | raw | diff to current |
| 2013-01-13 |
Nilay Vaish | x86: Changes to decoder, corrects 9376 |
blob | commitdiff | raw | diff to current |
| 2013-01-07 |
Andreas Sandberg | arch: Move the ISA object to a separate section |
blob | commitdiff | raw | diff to current |
| 2013-01-07 |
Andreas Sandberg | arch: Make the ISA class inherit from SimObject |
blob | commitdiff | raw | diff to current |
| 2011-04-15 |
Nathan Binkert | trace: reimplement the DTRACE function so it doesn... |
blob | commitdiff | raw | diff to current |
| 2010-11-08 |
Ali Saidi | ARM: Add checkpointing support |
blob | commitdiff | raw | diff to current |
| 2010-08-23 |
Min Kyu Jeong | ARM: Clean up flattening for SPSR adding |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Move the ISA "clear" function into isa.cc. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Some TLB bug fixes. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Move Miscreg functions out of isa.hh |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Implement the ARM TLB/Tablewalker. Needs performan... |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Implement ARM CPU interrupts |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Make various bits of the FP control registers... |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Make MPIDR return 0 and ignore writes. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Set the value of the MVFR0 and MVFR1 registers. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Handle accesses to TLBTR. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Convert the CP15 registers from MPU to MMU. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Add some support for wfi/wfe/yield/etc |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Ali Saidi | ARM: Add a traceflag to print cpsr |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Ignore attempts to disable coprocessors that aren... |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Allow flattening into any mode. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Make the MPUIR register report that 1 unified... |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Ignore/warn when CSSELR or CCSIDR are accessed. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Add support for the clidr register. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Implement a stub of CPACR. |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Actually write the value of sctlr in ISA.clear(). |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Implement a function to decode CP15 registers... |
blob | commitdiff | raw | diff to current |
| 2010-06-02 |
Gabe Black | ARM: Track the current ISA mode using the PC. |
blob | commitdiff | raw | diff to current |
| 2010-01-19 |
Derek Hower | merge |
blob | commitdiff | raw | diff to current |
| 2009-11-15 |
Gabe Black | ARM: Hook up the moded versions of the SPSR. |
blob | commitdiff | raw | diff to current |
| 2009-11-11 |
Gabe Black | Merge with the head. |
blob | commitdiff | raw | diff to current |
| 2009-11-11 |
Gabe Black | ARM: Implement fault classes. |
blob | commitdiff | raw | diff to current |
| 2009-11-09 |
Nathan Binkert | automerge |
blob | commitdiff | raw | diff to current |
| 2009-11-08 |
Gabe Black | ARM: Support forcing load/store multiple to use user... |
blob | commitdiff | raw | diff to current |
| 2009-11-08 |
Gabe Black | ARM: Add in more bits for the mon mode. |
blob | commitdiff | raw | diff to current |
| 2009-11-08 |
Gabe Black | ARM: Initialize processes in user mode. |
blob | commitdiff | raw | diff to current |
| next |
projects / gem5.git / history