arch-power: Add doubleword modulo instructions
[gem5.git] / src / arch / arm /
2021-02-11 Giacomo Travagliniarch-arm: Fix CPTR_EL2 writes
2021-02-10 Hoa Nguyenarch-arm,arch-riscv,arch-x86: Add units to stats
2021-02-09 Gabe Blacksim: Get rid of the IsConforming type trait template.
2021-02-09 Gabe Blackarch,sim: Use VPtr<> instead of Addr in system call...
2021-02-06 Gabe Blackarch,sim: Add a UintPtr type to the ABI types for GuestABI.
2021-02-05 Gabe Blackarch,cpu: Move a Decode DPRINTF into the arch Decoder...
2021-02-04 Bobby R. BruceMerge "misc: Merge branch v20.1.0.3 hotfix into develop...
2021-02-04 Earl Oufastmodel: fix cntfrq in A76
2021-02-03 Bobby R. Brucemisc: Merge branch v20.1.0.3 hotfix into develop
2021-02-03 Giacomo Travagliniarch-arm: Add destRegIdxArr arrays to TME instructions
2021-02-03 Gabe Blackarch-arm,cpu: Use getEMI() in more places.
2021-02-03 Gabe Blackarch-arm,cpu: Introduce a getEMI virtual method on...
2021-02-03 Gabe Blackarch: Templatize the BasicDecodeCache.
2021-02-02 Adrian Herreraarch-arm: don't expose FEAT_VHE by default
2021-02-02 Gabe Blackext: Update pybind11 to version 2.6.2.
2021-02-02 Earl Oufastmodel: add interface to update system counter freq
2021-02-02 Earl Oufastmodel: create base class for EVS CPU
2021-02-01 Earl Oufastmodel: remove incorrect cntfrq update
2021-01-31 Gabe Blackarch: Stop using switching header files in ISA specific...
2021-01-29 Gabe Blackarch-arm: Fix style in decoder.hh.
2021-01-28 Gabe Blackarch,base,mem,sim: Fix style in base/types.hh and remov...
2021-01-27 Andreas Sandbergarch, mem, cpu, systemc: Remove Python 2.7 glue code
2021-01-26 Gabe Blackarch-arm: Don't use TheISA in the ARM implementation.
2021-01-25 Giacomo Travagliniarch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopD...
2021-01-24 Andreas Sandbergarch-arm, dev-arm: Consistently use ISO prefixes
2021-01-23 Gabe Blackarch-arm: Stop "using namespace std"
2021-01-23 Giacomo Travagliniarch-arm: Fix Compare and Swap Pair instructions
2021-01-22 Andreas Sandbergarch-arm, dev-arm: Remove Python 2 compatibility code
2021-01-20 Gabe Blackarm: Use the "reg" ABI for gem5 ops.
2021-01-19 Gabe Blackarm: Export the mostly generic syscall ABI.
2021-01-19 Gabe Blackarm: Use local src and dest reg index arrays.
2021-01-18 Giacomo Travagliniarch-arm: dtb_addr is already encoding the loadAddrOffset
2021-01-13 Ciro Santilliarch-arm: inform bootloader of kernel position with...
2020-12-21 Gabe Blackscons,fastmodel: Change how ARM license slots are throt...
2020-12-16 Gabe Blackarm: Fix style in the ISA templates.
2020-12-11 muptonarm,kvm: missed rename of MISCREG_HYP in kvm/armv8_cpu.cc
2020-11-26 Ciro Santilliarch-arm: add official names to all PMU events
2020-11-26 Curtis Dunhamarch-arm: Add ID_MMFR4{,EL1} system registers
2020-11-26 Bobby R. BruceMerge "misc: Merge branch hotfix v20.1.0.2 branch into...
2020-11-25 Giacomo Travagliniarch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure...
2020-11-25 Giacomo Travagliniarch-arm: Add SECURE_RD/WR flags to miscRegInfo
2020-11-25 Ciro Santilliarch-arm: implement the aarch64 ID_ISAR6_EL1 miscregister
2020-11-24 Gabe Blackarm: Use the common pseudoInst dispatch function.
2020-11-23 Ciro Santilliarch-arm: serialize miscregs as a map
2020-11-19 Giacomo Travaglinifastmodel: Replace xrange with range to be python3...
2020-11-19 Giacomo Travaglinifastmodel: Use BaseMMU in the CortexR52 wrapper
2020-11-17 Jordi Vaqueroarch-arm: Implementation ARMv8.1 RDMA
2020-11-17 Gabe Blackfastmodel: Wrap the PL330 DMA controller fast model.
2020-11-16 Bobby R. Brucemisc: Merge branch hotfix v20.1.0.2 branch into develop
2020-11-16 Ciro Santilliarch-arm: move serialize and unserialize definition...
2020-11-06 Gabe Blackarch,cpu: Enforce using accessors to get at src/destRegIdx.
2020-11-04 Gabe Blackarm: Get rid of some unused instruction templates.
2020-11-03 Giacomo Travagliniarch-arm: Do not use _flushMva for TLBI IPA
2020-11-03 Giacomo Travagliniarch-arm: TlbEntry flush to be considered as functional...
2020-11-03 Giacomo Travagliniarch-arm: Fix implementation of TLBI_VMALL instructions
2020-11-03 Giacomo Travagliniarch-arm: Add el2Enabled cached variable
2020-11-03 Giacomo Travaglinicpu, fastmodel: Remove the old getDTBPtr/getITBPtr...
2020-11-03 Yu-hsin Wangdev-arm: Fix VExpressFastmodel timer configs
2020-11-02 Giacomo Travaglinikvm, arm: Add parameter to force simulation of Gicv2
2020-10-30 Gabe Blackmisc: Delete the now unnecessary create methods.
2020-10-29 Gabe Blackarch,sim: Handle KVM SE page faults with workload events.
2020-10-28 Gabe Blackarm: Implement an SE workload for Linux and FreeBSD.
2020-10-24 Gabe Blackfastmodel: Fix up for the new standardized create(...
2020-10-23 Giacomo Travagliniarch-arm: Fix implementation of TLBI ALLEx instructions
2020-10-23 Giacomo Travagliniarch-arm: Rewrite the TLB flushing interface
2020-10-23 Giacomo Travagliniarch-arm: Reimplement TLB::flushAll
2020-10-23 Giacomo Travagliniarch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for...
2020-10-23 Gabe Blackmisc: Replace enable_if<>::type with enable_if_t<>.
2020-10-21 Giacomo Travagliniarch-arm: Replace any getDTBPtr/getITBPtr usage
2020-10-21 Giacomo Travaglinimisc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
2020-10-19 Gabe Blackmisc: Wrap __attribute__((aligned())) in a macro in...
2020-10-19 Gabe Blackmisc: Use compiler.hh macros when available.
2020-10-17 Giacomo Travagliniarch-arm: Implement ArmPMU DTB generation
2020-10-17 Giacomo Travaglinidev-arm, fastmodel: Rewrite Gic.interruptCells
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects.
2020-10-14 Jordi Vaqueroarch-arm: Implement Armv8.2-LPA
2020-10-14 Jordi Vaqueroarch-arm: Implement Armv8.2-LVA
2020-10-14 Gabe Blackfastmodel: Update to c++14, and add some missing consts.
2020-10-13 Gabe Blackfastmodel: Add a wrapper for the CortexR52.
2020-10-08 Giacomo Travagliniarch-arm: Default ArmSystem to AArch64
2020-10-07 Giacomo Travaglinifastmodel: Add IrisMMU model
2020-10-07 Giacomo Travagliniarch: Add generic BaseMMU
2020-10-06 Hoa Nguyenarch-arm: Replace call to `tmpnam()` by a deterministic one
2020-10-06 Pierre Ayoubarch-arm: Add recursion for DTB entry generation inside...
2020-10-01 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-30 Giacomo Travagliniarch-arm: Using new "raw" memhelpers
2020-09-29 Timothy Hayesarch-arm: Instantiate a single HTM checkpoint at ISA...
2020-09-28 Gabe Blackmisc: Update attribute syntax, and reorganize compiler.hh.
2020-09-28 Gabe Blackarch,base,cpu,dev: Get rid of the M5_DUMMY_RETURN macro.
2020-09-28 Gabe Blackarm,base,gpu: Use std::make_unique instead of m5::make_...
2020-09-25 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-24 Gabe Blackfastmodel: Update the IRIS ThreadContext base class.
2020-09-24 Gabe Blackfastmodel: Update for the isa_traits.hh changes.
2020-09-22 Giacomo Travagliniarch-arm: TLBI ALLE2IS should broadcast to the IS domain
2020-09-22 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-20 Gabe Blackarch,cpu,sim: Route system calls through the workload.
2020-09-17 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-16 Gabe Blackarch,cpu: Get rid of the IsMemRef StaticInst flag.
2020-09-16 Gabe Blackarch,cpu: Rearrange StaticInst flags for memory barriers.
2020-09-16 Gabe Blackarm: Use zero initialization for the BigRegVect types.
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