sim: Break the eventq.hh dependency in core.hh.
[gem5.git] / src / arch / generic /
2020-11-16 Bobby R. Brucemisc: Merge branch hotfix v20.1.0.2 branch into develop
2020-10-29 Gabe Blackarch: Move many of the generic files outside an NULL...
2020-10-29 Gabe Blackarch,sim: Handle KVM SE page faults with workload events.
2020-10-23 Gabe Blackmisc: Replace enable_if<>::type with enable_if_t<>.
2020-10-21 Giacomo Travagliniarch: Use getTlb in BaseMMU to reduce boilerplate
2020-10-21 Giacomo Travaglinimisc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects.
2020-10-07 Giacomo Travagliniarch: Add generic BaseMMU
2020-10-01 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-30 Giacomo Travagliniarch: Add raw read/writeMem helpers
2020-09-10 Shivani Parekhmisc: Replaced master/slave terminology
2020-09-09 Gabe Blackarch: Add a virtual destructor to BaseHTMCheckpoint.
2020-09-08 Andreas Sandbergbase, sim: Make ByteOrder into a ScopedEnum accessible...
2020-09-02 Timothy Hayesarch: Add uReset helper to UPCState
2020-09-02 Timothy Hayesarch, mem: Initial Hardware Transactional Memory implem...
2020-09-01 Nikos Nikolerisarch: Remove unused variable pcbb from ThreadInfo
2020-08-28 Gabe Blackmisc: Clean up usage of arch/isa_traits.hh.
2020-08-26 Emily Brickeyarch: update port terminology
2020-08-25 Gabe Blackcpu,arch: Delegate fetching ROM microops to the decoder.
2020-08-20 Gabe Blackarch: Make ThreadInfo::curThreadInfo virtual, protected.
2020-08-20 Gabe Blackarch: Remove the "inline" keyword in ThreadInfo.
2020-08-20 Gabe Blackarch: Get the byte order from sys and not TheISA::.
2020-08-20 Gabe Blackarch: Don't add contents to the TheISA namespace in...
2020-08-20 Gabe Blackarch: Fix a small style issue in Linux::ThreadInfo.
2020-08-20 Gabe Blackarch: Create a base class for decoders.
2020-07-04 Gabe Blacksim: Retrofit the VPtr type.
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-12 Gabe Blackarch,cpu: Add a setThreadContext method to the ISA...
2020-06-11 Gabe Blackarch,cpu: Change setCPU to setThreadContext in Interrupts.
2020-06-09 Gabe Blackarch,base,cpu,kerm,sim: Build a symbol table for object...
2020-06-08 Bobby R. Brucemisc: Merge hotfix v20.0.0.2 into develop
2020-06-02 Bobby R. Brucemisc: Merge branch version update into develop
2020-06-02 Bobby R. Brucemisc: Merge in 'hotfix-m5-tick-rounding-error'
2020-05-28 Bobby R. BruceMerge branch 'release-staging-v20.0.0.0' into develop
2020-05-28 Bobby R. Brucemisc: Merge branch 'release-staging-v20.0.0.0' into...
2020-05-19 Gabe Blackarch,base,cpu,kern,sim: Encapsulate symbols in a class.
2020-04-23 Jordi Vaqueroarch: Fix VecReg container alignement to 128bits view
2020-04-22 Gabe Blackarch,sim,kern,dev,cpu: Create a Workload SimObject.
2020-04-15 Giacomo Travagliniarch, cpu: Add a takeOverFrom method for switching...
2020-03-11 Gabe Blackconfig,arch,cpu,kern,sim: Extract kernel information...
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-20 Gabe Blackarch: Convert the static constexpr SIZE in vec_reg...
2020-02-19 Giacomo Travagliniarch, arch-arm: Use BaseISA in RenameMode interface
2020-02-18 Gabe Blackarch: Delete authors lists from generic arch files.
2020-02-11 Gabe Blackarch: Get rid of the generic mmapped IPR mechanism.
2020-02-05 Gabe Blackarch: Introduce a base class for ISA classes.
2020-02-01 Gabe Blackarch,base,cpu: Add some default constructors/operators...
2020-01-11 Gabe Blackarch: Make the generic micropc enabled PCState set...
2020-01-07 Gabe Blackarch,sim: Stop decoding the pseudo inst subfunc value.
2020-01-06 Gabe Blackarch,sim: Use the guest ABI mechanism with pseudo instr...
2019-12-10 Gabe Blacksim,arch: Collapse the ISA specific versions of m5Syscall.
2019-11-18 Gabe Blackarch: Make and use endian specific versions of the...
2019-10-19 Gabe Blackarch: Make a base class for Interrupts.
2019-10-18 Gabe Blackarch: Get rid of the unused GenericTLB.
2019-09-23 Jordi Vaquerocpu, mem: Changing AtomicOpFunctor* for unique_ptr...
2019-09-18 Gabe Blackarch, x86: Rework the debug faults and microops.
2019-08-28 Gabe Blackmem: Eliminate the Base(Slave|Master)Port classes.
2019-08-21 Ciro Santilliarch-arm, cpu: fix ARM ubsan build on GCC 7.4.0
2019-08-09 Tony Gutierrezarch: Bump MaxVecRegLenInBytes to 4096
2019-05-30 Gabe Blackarch, base, sim: Replace Copy(String)?(In|Out) with...
2019-05-29 Gabe Blackarch, base, dev, sim: Remove now unnecessary casts...
2019-04-28 Gabe Blackmem: Minimize the use of MemObject.
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using...
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE
2019-03-01 Andrea Mondellimem-cache: alias to mem::getMasterPort in TLB class
2019-02-23 Andreas Sandbergpython: Enforce absolute imports for Python 3 compatibility
2019-02-18 Ivan Pizarroarch-generic: Making base TLB class a MemObject
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
2018-10-17 Gabe Blackarch: Include some additional headers in arch/generic...
2018-10-12 Gabe Blackarch: Explicitly specify the endianness in the generic...
2018-10-02 Gabor Dozsaarch: Fix unserialization of VectorReg value
2018-06-14 Tuan Taarch: support issuing Atomic Mem Operation (AMO) requests
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2018-03-27 Gabe Blackarch: cpu: Make the ExtMachInst type a template argumen...
2017-12-22 Gabe Blackarch,cpu: "virtualize" the TLB interface.
2017-12-13 Gabe Blackarm,sparc,x86,base,cpu,sim: Replace the Twin(32|64...
2017-12-04 Gabe Blackmisc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-10-13 Nikos Nikolerismem: Signal the local monitor when clearing the global...
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2017-07-05 Rekai Gonzalez-Alb... arch: added generic vector register
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing
2017-06-22 Paul Rosenfeldarm,sim: fix context switch stats dumps for ARM64/Linux
2017-02-27 Brandon Pottersyscall_emul: [PATCH 15/22] add clone/execve for thread...
2017-02-27 Andreas Sandbergarch: Include generated decoder header after normal...
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-08-15 Nikos Nikoleriscpu, arch: fix the type used for the request flags
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements
2016-01-18 Steve Reinhardtcpu. arch: add initiateMemRead() to ExecContext interface
2016-01-18 Steve Reinhardtarch: don't call *Timing functions from *Atomic versions
2015-10-12 Andreas Hanssonmisc: Add explicit overrides and fix other clang >...
2015-10-12 Andreas Hanssonmisc: Remove redundant compiler-specific defines
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-04-30 Ruslan Bukinarch, base, dev, kern, sym: FreeBSD support
2015-02-11 Andreas Sandbergsim: Move the BaseTLB to src/arch/generic/
2014-11-24 Alexandru Dutukvm, x86: Adding support for SE mode execution
2014-11-14 Andreas Hanssonarm: Fixes based on UBSan and static analysis
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
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