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[gem5.git] / src / arch / null / registers.hh

2020-02-24	Bobby R. Bruce	misc: Merged release-staging-v19.0.0.0 into develop	blob \| commitdiff \| raw
2020-02-18	Gabe Black	arch: Delete authors lists from the null arch files.	blob \| commitdiff \| raw
2019-02-01	Gabe Black	cpu, arch: Replace the CCReg type with RegVal.	blob \| commitdiff \| raw \| diff to current
2019-01-31	Gabe Black	null: Get rid of some register type definitions.	blob \| commitdiff \| raw \| diff to current
2019-01-31	Gabe Black	arch: cpu: Rename FloatRegBits to FloatReg.	blob \| commitdiff \| raw \| diff to current
2019-01-30	Giacomo Gabrielli	arch,cpu: Add vector predicate registers	blob \| commitdiff \| raw \| diff to current
2019-01-24	Gabe Black	base: arch: Get rid of the now unused FloatRegVal type.	blob \| commitdiff \| raw \| diff to current
2019-01-16	Gabe Black	arch: Make the ISA register types aliases for the globa...	blob \| commitdiff \| raw \| diff to current
2018-11-05	Gabe Black	null: Claim to use 64 bit floating point registers.	blob \| commitdiff \| raw \| diff to current
2017-07-05	Rekai Gonzalez-Alb...	cpu: Added interface for vector reg file	blob \| commitdiff \| raw \| diff to current
2017-07-05	Nathanael Premillieu	arch, cpu: Architectural Register structural indexing	blob \| commitdiff \| raw \| diff to current
2015-07-28	Nilay Vaish	revert 5af8f40d8f2c	blob \| commitdiff \| raw \| diff to current
2015-07-26	Nilay Vaish	cpu: implements vector registers	blob \| commitdiff \| raw \| diff to current
2013-10-15	Yasuko Eckert	cpu: add a condition-code register class	blob \| commitdiff \| raw \| diff to current
2013-09-04	Andreas Hansson	arch: Resurrect the NOISA build target and rename it...	blob \| commitdiff \| raw \| diff to current

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