arch-riscv: Stop "using namespace std"
[gem5.git] / src / arch / riscv / isa / decoder.isa
2021-01-23 Gabe Blackarch-riscv: Stop "using namespace std"
2020-11-16 Bobby R. Brucemisc: Merge branch hotfix v20.1.0.2 branch into develop
2020-10-27 Giacomo Travagliniarch-riscv: Replace any getDTBPtr/getITBPtr usage
2020-10-01 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-25 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-22 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-17 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-16 Gabe Blackarch,cpu: Rearrange StaticInst flags for memory barriers.
2020-04-29 Nils Asmussenarch-riscv: let FPU instructions fault if status.FS...
2020-04-29 Nils Asmussenarch-riscv: make uret,sret,mret SerializeAfter,NonSpecu...
2020-04-29 Nils Asmussenarch-riscv: make accesses to CSRs SerializeAfter.
2020-04-29 Nils Asmussenarch-riscv: fault according to status.{TVM,TSK,TW}.
2020-04-29 Nils Asmussenarch-riscv: added dummy implementation of wfi instruction.
2020-04-29 Nils Asmussenarch-riscv: implement sfence.vma to flush TLBs.
2020-03-26 Nils Asmussenarch-riscv: added support for pseudo instructions.
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-18 Gabe Blackriscv: Delete authors lists from riscv files.
2020-02-10 Gabe Blackriscv: Cast to float explicitly when comparing a float...
2019-11-26 Ian Jiangarch-riscv: Fix immediate decoding for integer shift...
2019-11-26 Ian Jiangarch-riscv: Fix disassembling for fence and fence.i
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of operand list for compr...
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of immediate for U-type...
2019-05-03 Avishai Tvilaarch-riscv,isa: Fix for compressed jump (c_j) imm
2019-02-08 Tuan Tariscv: fix AMO, LR and SC instructions
2019-02-06 Tuan Tariscv: remove NonSpeculative flag from fence inst
2019-01-31 Gabe Blackriscv: Get rid of some ISA specific register types.
2018-07-28 Alec Roelkearch-riscv: Add xret instructions
2018-07-28 Alec Roelkearch-riscv: Add support for trap value register
2018-07-09 Austin Harrisarch-riscv: Fix the srlw and srliw instructions.
2018-05-12 Alec Roelkearch-riscv: Update CSR implementations
2018-03-20 Tuan Tariscv: throw IllegalInstFault when decoding invalid...
2018-02-19 Alec Roelkearch-riscv: Fix compressed branch op offset
2018-01-16 Alec Roelkearch-riscv: Fix floating-poing op classes
2018-01-16 Alec Roelkearch-riscv: Fix floating-point conversion bugs
2018-01-10 Alec Roelkearch-riscv: Make use of ImmOp's polymorphism
2017-11-29 Alec Roelkearch-riscv: Move parts of mem insts out of ISA
2017-07-14 Gabe Blackriscv: Disambiguate between the C and C++ versions...
2017-07-14 Alec Roelkeriscv: Fix bugs with RISC-V decoder and detailed CPUs
2017-07-11 Alec Roelkearch-riscv: Add support for compressed extension RV64C
2017-07-11 Alec Roelkearch-riscv: Restructure ISA description
2017-04-05 Alec Roelkeriscv: fix Linux problems with LR and SC ops
2016-11-30 Alec Roelkeriscv: [Patch 7/5] Corrected LRSC semantics
2016-11-30 Alec Roelkeriscv: [Patch 4/5] Added RISC-V atomic memory extension...
2016-11-30 Alec Roelkeriscv: [Patch 3/5] Added RISCV floating point extension...
2016-11-30 Alec Roelkeriscv: [Patch 2/5] Added RISC-V multiply extension...
2016-11-30 Alec Roelkearch: [Patch 1/5] Added RISC-V base instruction set...