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arch: cpu: Rename *FloatRegBits* to *FloatReg*.
[gem5.git] / src / arch / riscv / registers.hh
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*. blob | commitdiff | raw
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers blob | commitdiff | raw | diff to current
2019-01-24 Gabe Blackbase: arch: Get rid of the now unused FloatRegVal type. blob | commitdiff | raw | diff to current
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa... blob | commitdiff | raw | diff to current
2018-07-28 Alec Roelkearch-riscv: Add xret instructions blob | commitdiff | raw | diff to current
2018-05-12 Alec Roelkearch-riscv: Update CSR implementations blob | commitdiff | raw | diff to current
2018-01-05 Alec Roelkearch-riscv: Correct syscall argument reg count blob | commitdiff | raw | diff to current
2017-07-17 Alec Roelkeriscv: Define register index constants using literals blob | commitdiff | raw | diff to current
2017-07-14 Alec Roelkeriscv: Add unused attribute to some registers.hh constants blob | commitdiff | raw | diff to current
2017-07-11 Alec Roelkearch-riscv: Restructure ISA description blob | commitdiff | raw | diff to current
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file blob | commitdiff | raw | diff to current
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing blob | commitdiff | raw | diff to current
2017-04-05 Alec Roelkeriscv: add remote gdb support blob | commitdiff | raw | diff to current
2017-03-09 Brandon Pottersyscall-emul: Rewrite system call exit code blob | commitdiff | raw | diff to current
2016-11-30 Alec Roelkeriscv: [Patch 4/5] Added RISC-V atomic memory extension... blob | commitdiff | raw | diff to current
2016-11-30 Alec Roelkeriscv: [Patch 3/5] Added RISCV floating point extension... blob | commitdiff | raw | diff to current
2016-11-30 Alec Roelkearch: [Patch 1/5] Added RISC-V base instruction set... blob | commitdiff | raw | diff to current