2019-10-09 |
Gabe Black | base: Rename Section to Segment, and some of its members. |
tree | commitdiff |
2019-08-23 |
Alec Roelke | arch-riscv: fix GDB register cache |
tree | commitdiff |
2019-08-21 |
Yifei Liu | arch-riscv: Update register file |
tree | commitdiff |
2019-05-30 |
Gabe Black | arch, base, cpu, gpu, sim: Merge getMemProxy and getVir... |
tree | commitdiff |
2019-05-29 |
Ciro Santilli | sim-se: add a release parameter to Process.py |
tree | commitdiff |
2019-05-21 |
Brandon Potter | sim-se: change syscall function signature |
tree | commitdiff |
2019-05-20 |
Gabe Black | riscv: Add an object file loader for linux. |
tree | commitdiff |
2019-05-04 |
Alec Roelke | arch-riscv: Implement MHARTID CSR |
tree | commitdiff |
2019-05-03 |
Avishai Tvila | arch-riscv,isa: Fix for compressed jump (c_j) imm |
tree | commitdiff |
2019-04-30 |
Gabe Black | arch: Stop using TheISA within the ISAs. |
tree | commitdiff |
2019-04-28 |
Gabe Black | arch, sim: Simplify the AuxVector type. |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Don't assume SimObjects live in the global... |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fix AMO, LR and SC instructions |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fixed syscall return value |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: ignore nanosleep syscall |
tree | commitdiff |
2019-02-08 |
Tuan Ta | arch-riscv: initialize RISC-V's thread pointer register... |
tree | commitdiff |
2019-02-07 |
Austin Harris | arch-riscv: Enable support for riscv 32-bit in SE mode. |
tree | commitdiff |
2019-02-06 |
Tuan Ta | riscv: remove NonSpeculative flag from fence inst |
tree | commitdiff |
2019-02-06 |
Tuan Ta | arch-riscv: Initialize interrupt mask |
tree | commitdiff |
2019-02-05 |
Andrea Mondelli | misc: added missing override specifier |
tree | commitdiff |
2019-02-05 |
Austin Harris | riscv: Get rid of ISA specific register types in Interr... |
tree | commitdiff |
2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
tree | commitdiff |
2019-01-31 |
Gabe Black | riscv: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
tree | commitdiff |
2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
tree | commitdiff |
2019-01-24 |
Gabe Black | base: arch: Get rid of the now unused FloatRegVal type. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add syscalls related to polling |
tree | commitdiff |
2019-01-16 |
Gabe Black | arch: Make the ISA register types aliases for the globa... |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Add interrupt handling |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Fix reset function and style |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | sim-se: Refactor clone to avoid most ifdefs |
tree | commitdiff |
2018-09-19 |
Brandon Potter | syscall_emul: expand AuxVector class |
tree | commitdiff |
2018-07-28 |
Alec Roelke | arch-riscv: Add xret instructions |
tree | commitdiff |
2018-07-28 |
Alec Roelke | arch-riscv: Add support for trap value register |
tree | commitdiff |
2018-07-28 |
Alec Roelke | arch-riscv: Add support for fault handling |
tree | commitdiff |
2018-07-09 |
Robert | arch-riscv: enable rudimentary fs simulation |
tree | commitdiff |
2018-07-09 |
Austin Harris | arch-riscv: Fix the srlw and srliw instructions. |
tree | commitdiff |
2018-06-11 |
Giacomo Travaglini | misc: Using smart pointers for memory Requests |
tree | commitdiff |
2018-06-11 |
Giacomo Travaglini | misc: Substitute pointer to Request with aliased RequestPtr |
tree | commitdiff |
2018-05-12 |
Alec Roelke | arch-riscv: Update CSR implementations |
tree | commitdiff |
2018-03-27 |
Gabe Black | arch: cpu: Make the ExtMachInst type a template argumen... |
tree | commitdiff |
2018-03-26 |
Gabe Black | arch: Fix all override related warnings. |
tree | commitdiff |
2018-03-26 |
Gabe Black | arch: Add a virtual asBytes function to the StaticInst... |
tree | commitdiff |
2018-03-20 |
Tuan Ta | riscv: throw IllegalInstFault when decoding invalid... |
tree | commitdiff |
2018-02-19 |
Alec Roelke | arch-riscv: Fix compressed branch op offset |
tree | commitdiff |
2018-01-29 |
Gabe Black | riscv: Add overrides to various StaticInst methods. |
tree | commitdiff |
2018-01-20 |
Gabe Black | arch, mem: Make the page table lookup function return... |
tree | commitdiff |
2018-01-20 |
Gabe Black | sim, arch, base: Refactor the base remote GDB class. |
tree | commitdiff |
2018-01-19 |
Gabe Black | arch, mem, sim: Consolidate and rename the SE mode... |
tree | commitdiff |
2018-01-16 |
Alec Roelke | arch-riscv: Fix floating-poing op classes |
tree | commitdiff |
2018-01-16 |
Alec Roelke | arch-riscv: Fix floating-point conversion bugs |
tree | commitdiff |
2018-01-15 |
Gabe Black | arch: Fix a fatal_if in most of the arch's process... |
tree | commitdiff |
2018-01-11 |
Alec Roelke | arch-riscv: Don't crash when printing unknown CSRs |
tree | commitdiff |
2018-01-11 |
Gabe Black | arch,mem: Remove the default value for page size. |
tree | commitdiff |
2018-01-11 |
Gabe Black | arch,mem: Move page table construction into the arch... |
tree | commitdiff |
2018-01-10 |
Alec Roelke | arch-riscv: Make use of ImmOp's polymorphism |
tree | commitdiff |
2018-01-10 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of... |
tree | commitdiff |
2018-01-05 |
Tuan Ta | arch-riscv: Ignore sched_yield syscall in SE mode |
tree | commitdiff |
2018-01-05 |
Tuan Ta | arch-riscv: Ignore set_robust_list and get_robust_list... |
tree | commitdiff |
2018-01-05 |
Tuan Ta | arch-riscv: Add an implementation of set_tid_address... |
tree | commitdiff |
2018-01-05 |
Alec Roelke | arch-riscv: Correct syscall argument reg count |
tree | commitdiff |
2018-01-04 |
Alec Roelke | arch-riscv: Remove "magic" syscall number constant |
tree | commitdiff |
2017-12-23 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA... |
tree | commitdiff |
2017-12-23 |
Gabe Black | riscv,x86: Stop using the arch Nop machine instruction... |
tree | commitdiff |
2017-12-22 |
Gabe Black | arch,cpu: "virtualize" the TLB interface. |
tree | commitdiff |
2017-12-14 |
Alec Roelke | arch-riscv: Define AT_RANDOM properly |
tree | commitdiff |
2017-12-14 |
Alec Roelke | arch-riscv: Increase maximum stack size |
tree | commitdiff |
2017-12-13 |
Gabe Black | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp... |
tree | commitdiff |
2017-12-07 |
Alec Roelke | arch-riscv: Move compressed ops out of ISA |
tree | commitdiff |
2017-12-04 |
Gabe Black | misc: Rename misc.(hh|cc) to logging.(hh|cc) |
tree | commitdiff |
2017-11-30 |
Alec Roelke | arch-riscv: use sext rather than manual masks |
tree | commitdiff |
2017-11-30 |
Alec Roelke | arch-riscv: Remove spaces around ea_code |
tree | commitdiff |
2017-11-29 |
Alec Roelke | arch-riscv: Add missing license paragraphs |
tree | commitdiff |
2017-11-29 |
Alec Roelke | arch-riscv: Remove static parts of AMOs out of ISA |
tree | commitdiff |
2017-11-29 |
Alec Roelke | arch-riscv: Move parts of mem insts out of ISA |
tree | commitdiff |
2017-11-29 |
Alec Roelke | arch-riscv: Move unknown out of ISA description |
tree | commitdiff |
2017-11-29 |
Alec Roelke | arch-riscv: Move standard ops out of ISA |
tree | commitdiff |
2017-11-28 |
Alec Roelke | arch-riscv: Move static_inst into a directory |
tree | commitdiff |
2017-11-22 |
Alec Roelke | arch-riscv: Add missing system calls |
tree | commitdiff |
2017-11-07 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl... |
tree | commitdiff |
2017-11-02 |
Gabe Black | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize... |
tree | commitdiff |
2017-10-17 |
Gabe Black | scons: Stop generating inc.d in the isa parser. |
tree | commitdiff |
2017-10-13 |
Nikos Nikoleris | mem: Signal the local monitor when clearing the global... |
tree | commitdiff |
2017-09-11 |
Gabe Black | stats: Get rid of some kernel stats related cruft. |
tree | commitdiff |
2017-07-17 |
Alec Roelke | riscv: Define register index constants using literals |
tree | commitdiff |
2017-07-14 |
Gabe Black | riscv: Disambiguate between the C and C++ versions... |
tree | commitdiff |
2017-07-14 |
Alec Roelke | riscv: Fix bugs with RISC-V decoder and detailed CPUs |
tree | commitdiff |
2017-07-14 |
Alec Roelke | riscv: Add unused attribute to some registers.hh constants |
tree | commitdiff |
2017-07-11 |
Alec Roelke | arch-riscv: Add support for compressed extension RV64C |
tree | commitdiff |
2017-07-11 |
Alec Roelke | arch-riscv: Restructure ISA description |
tree | commitdiff |
2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Added interface for vector reg file |
tree | commitdiff |
2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Simplify the rename interface and use RegId |
tree | commitdiff |
2017-07-05 |
Nathanael Premillieu | arch, cpu: Architectural Register structural indexing |
tree | commitdiff |
2017-05-23 |
Alec Roelke | arch-riscv: Fix bad stack initialization |
tree | commitdiff |
2017-05-18 |
Gabe Black | base: Refactor the GDB code. |
tree | commitdiff |
2017-05-18 |
Brandon Potter | syscall_emul, riscv: add override keyword to RISCV... |
tree | commitdiff |
2017-04-11 |
Alec Roelke | riscv: Fix crashes with large or frequent mmaps |
tree | commitdiff |
2017-04-05 |
Alec Roelke | riscv: fix Linux problems with LR and SC ops |
tree | commitdiff |
2017-04-05 |
Alec Roelke | riscv: fix compatibility with Linux toolchain |
tree | commitdiff |
next |