2020-11-02 |
Matthew Poremba | arch-x86: Make CPUID vendor string a param |
tree | commitdiff |
2020-11-02 |
Giacomo Travaglini | kvm, arm: Add parameter to force simulation of Gicv2 |
tree | commitdiff |
2020-10-30 |
Gabe Black | misc: Delete the now unnecessary create methods. |
tree | commitdiff |
2020-10-29 |
Gabe Black | arch: Move many of the generic files outside an NULL... |
tree | commitdiff |
2020-10-29 |
Gabe Black | arch,sim: Handle KVM SE page faults with workload events. |
tree | commitdiff |
2020-10-29 |
Gabe Black | x86,kvm: Use the new workload event to trigger KVM... |
tree | commitdiff |
2020-10-29 |
Gabe Black | mips: Implement an SE workload for Linux. |
tree | commitdiff |
2020-10-29 |
Gabe Black | riscv: Implement an SE workload for Linux. |
tree | commitdiff |
2020-10-28 |
Gabe Black | x86,scons: De-indent the main x86 SConscript file. |
tree | commitdiff |
2020-10-28 |
Gabe Black | x86: Separate system call tables into their own files. |
tree | commitdiff |
2020-10-28 |
Gabe Black | arm: Implement an SE workload for Linux and FreeBSD. |
tree | commitdiff |
2020-10-28 |
Gabe Black | arch: Re-add copyrights that were accidentally removed. |
tree | commitdiff |
2020-10-27 |
Giacomo Travaglini | arch-x86: Replace any getDTBPtr/getITBPtr usage |
tree | commitdiff |
2020-10-27 |
Giacomo Travaglini | arch-sparc: Replace any getDTBPtr/getITBPtr usage |
tree | commitdiff |
2020-10-27 |
Giacomo Travaglini | arch-riscv: Replace any getDTBPtr/getITBPtr usage |
tree | commitdiff |
2020-10-27 |
Gabe Black | sparc: Remove support for Solaris SE mode. |
tree | commitdiff |
2020-10-27 |
Gabe Black | sparc: Implement an SE workload for Linux and Solaris. |
tree | commitdiff |
2020-10-26 |
Gabe Black | power: Implement an SE workload for Linux. |
tree | commitdiff |
2020-10-26 |
Gabe Black | x86: Delegate process loading to the EmuLinux workload. |
tree | commitdiff |
2020-10-24 |
Gabe Black | fastmodel: Fix up for the new standardized create(... |
tree | commitdiff |
2020-10-23 |
Giacomo Travaglini | arch-arm: Fix implementation of TLBI ALLEx instructions |
tree | commitdiff |
2020-10-23 |
Giacomo Travaglini | arch-arm: Rewrite the TLB flushing interface |
tree | commitdiff |
2020-10-23 |
Giacomo Travaglini | arch-arm: Reimplement TLB::flushAll |
tree | commitdiff |
2020-10-23 |
Giacomo Travaglini | arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for... |
tree | commitdiff |
2020-10-23 |
Gabe Black | misc: Replace enable_if<>::type with enable_if_t<>. |
tree | commitdiff |
2020-10-22 |
Gabe Black | x86: Move syscall handling for Linux into the EmuLinux... |
tree | commitdiff |
2020-10-22 |
Gabe Black | x86: Create an SEWorkload for x86 linux. |
tree | commitdiff |
2020-10-21 |
Gabe Black | misc: Fix a few accidental transitive includes. |
tree | commitdiff |
2020-10-21 |
Giacomo Travaglini | arch: Use getTlb in BaseMMU to reduce boilerplate |
tree | commitdiff |
2020-10-21 |
Giacomo Travaglini | arch-arm: Replace any getDTBPtr/getITBPtr usage |
tree | commitdiff |
2020-10-21 |
Giacomo Travaglini | misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB |
tree | commitdiff |
2020-10-20 |
Jason Lowe-Power | cpu-kvm, arch-x86: Fix KVM on Intel platforms |
tree | commitdiff |
2020-10-19 |
Gabe Black | misc: Wrap __attribute__((aligned())) in a macro in... |
tree | commitdiff |
2020-10-19 |
Gabe Black | misc: Use compiler.hh macros when available. |
tree | commitdiff |
2020-10-17 |
Giacomo Travaglini | arch-arm: Implement ArmPMU DTB generation |
tree | commitdiff |
2020-10-17 |
Giacomo Travaglini | dev-arm, fastmodel: Rewrite Gic.interruptCells |
tree | commitdiff |
2020-10-14 |
Gabe Black | misc: Standardize the way create() constructs SimObjects. |
tree | commitdiff |
2020-10-14 |
Jordi Vaquero | arch-arm: Implement Armv8.2-LPA |
tree | commitdiff |
2020-10-14 |
Jordi Vaquero | arch-arm: Implement Armv8.2-LVA |
tree | commitdiff |
2020-10-14 |
Gabe Black | fastmodel: Update to c++14, and add some missing consts. |
tree | commitdiff |
2020-10-13 |
Gabe Black | fastmodel: Add a wrapper for the CortexR52. |
tree | commitdiff |
2020-10-13 |
Gabe Black | arch: Use finditer in the (Sub)OperandList classes. |
tree | commitdiff |
2020-10-13 |
Gabe Black | arch: Pull the (Sub)OperandList classes into their... |
tree | commitdiff |
2020-10-12 |
Gabe Black | arch: Minor cleanup of imports in isa_parser.py. |
tree | commitdiff |
2020-10-12 |
Gabe Black | arch: Split utility methods/variables out of the ISA... |
tree | commitdiff |
2020-10-12 |
Gabe Black | arch: Split the operand types out of the ISA parser. |
tree | commitdiff |
2020-10-12 |
Gabe Black | arch: Move the ISA parser into a package. |
tree | commitdiff |
2020-10-09 |
Gabe Black | arch: Build the operand REs in the isa_parser on demand. |
tree | commitdiff |
2020-10-08 |
Giacomo Travaglini | arch-arm: Default ArmSystem to AArch64 |
tree | commitdiff |
2020-10-07 |
Gabe Black | sparc: Simplify the IntOp format slightly. |
tree | commitdiff |
2020-10-07 |
Gabe Black | sparc: Clean up some code in base.isa. |
tree | commitdiff |
2020-10-07 |
Giacomo Travaglini | fastmodel: Add IrisMMU model |
tree | commitdiff |
2020-10-07 |
Giacomo Travaglini | arch: Add generic BaseMMU |
tree | commitdiff |
2020-10-06 |
Hoa Nguyen | arch-arm: Replace call to `tmpnam()` by a deterministic one |
tree | commitdiff |
2020-10-06 |
Pierre Ayoub | arch-arm: Add recursion for DTB entry generation inside... |
tree | commitdiff |
2020-10-01 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.1.0.0' into... |
tree | commitdiff |
2020-09-30 |
Giacomo Travaglini | arch-x86: Add byteEnable mask in x86 memhelpers |
tree | commitdiff |
2020-09-30 |
Giacomo Travaglini | arch-arm: Using new "raw" memhelpers |
tree | commitdiff |
2020-09-30 |
Giacomo Travaglini | arch: Add raw read/writeMem helpers |
tree | commitdiff |
2020-09-30 |
Giacomo Travaglini | arch: Do value-initialization for MemOperand |
tree | commitdiff |
2020-09-29 |
Gabe Black | arch: Wrap a docstring in isa_parser.py. |
tree | commitdiff |
2020-09-29 |
Gabe Black | x86: Use the common pseudoInst dispatch function. |
tree | commitdiff |
2020-09-29 |
Timothy Hayes | arch-arm: Instantiate a single HTM checkpoint at ISA... |
tree | commitdiff |
2020-09-28 |
Gabe Black | misc: Update attribute syntax, and reorganize compiler.hh. |
tree | commitdiff |
2020-09-28 |
Gabe Black | arch,base,cpu,dev: Get rid of the M5_DUMMY_RETURN macro. |
tree | commitdiff |
2020-09-28 |
Gabe Black | arm,base,gpu: Use std::make_unique instead of m5::make_... |
tree | commitdiff |
2020-09-25 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.1.0.0' into... |
tree | commitdiff |
2020-09-24 |
Gabe Black | fastmodel: Update the IRIS ThreadContext base class. |
tree | commitdiff |
2020-09-24 |
Gabe Black | fastmodel: Update for the isa_traits.hh changes. |
tree | commitdiff |
2020-09-24 |
Kyle Roarty | gpu-compute: set exec_mask for permute,bpermute instruc... |
tree | commitdiff |
2020-09-22 |
Giacomo Travaglini | arch-arm: TLBI ALLE2IS should broadcast to the IS domain |
tree | commitdiff |
2020-09-22 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.1.0.0' into... |
tree | commitdiff |
2020-09-20 |
Gabe Black | arch,cpu,sim: Route system calls through the workload. |
tree | commitdiff |
2020-09-17 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.1.0.0' into... |
tree | commitdiff |
2020-09-16 |
Gabe Black | arch,cpu: Get rid of the IsMemRef StaticInst flag. |
tree | commitdiff |
2020-09-16 |
Gabe Black | arch,cpu: Rearrange StaticInst flags for memory barriers. |
tree | commitdiff |
2020-09-16 |
Gabe Black | arm: Use zero initialization for the BigRegVect types. |
tree | commitdiff |
2020-09-16 |
Gabe Black | mips,cpu: Eliminate the unused IsIndexed StaticInst... |
tree | commitdiff |
2020-09-15 |
Gabe Black | x86,cpu: Get rid of the unused IsCC StaticInst flag. |
tree | commitdiff |
2020-09-15 |
Gabe Black | mips,cpu: Get rid of the IsDpsOp StaticInst flag. |
tree | commitdiff |
2020-09-15 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.1.0.0' into... |
tree | commitdiff |
2020-09-15 |
Gabe Black | mips,cpu: Get rid of the IsIprAccess StaticInst flag. |
tree | commitdiff |
2020-09-15 |
Gabe Black | mips,cpu: Get rid of the IsERET StaticInst flag. |
tree | commitdiff |
2020-09-15 |
Gabe Black | mips,cpu: Get rid of the IsCondDelaySlot StaticInst... |
tree | commitdiff |
2020-09-15 |
Gabe Black | sparc,sim: Remove special handling of SPARC in the... |
tree | commitdiff |
2020-09-14 |
Andreas Sandberg | base, sim, mem, arch: Remove the dummy CPU in NULL |
tree | commitdiff |
2020-09-13 |
Giacomo Travaglini | arch-arm: Fix ArmISA namespace requirement for Arm KVM |
tree | commitdiff |
2020-09-11 |
Jason Lowe-Power | arch-arm: Initialize some cases of destReg |
tree | commitdiff |
2020-09-10 |
Shivani Parekh | misc: Replaced master/slave terminology |
tree | commitdiff |
2020-09-10 |
Iru Cai | arch-arm: just return the fault in twoEqualRegInst... |
tree | commitdiff |
2020-09-10 |
Iru Cai | arch-arm: Fix build errors with gcc 10.2 |
tree | commitdiff |
2020-09-10 |
Gabe Black | fastmodel: Add an ISA class which defers to IRIS. |
tree | commitdiff |
2020-09-10 |
Gabe Black | fastmodel: Create a fake "Interrupts" object for fast... |
tree | commitdiff |
2020-09-10 |
Bobby R. Bruce | arch-mips: Replaced `BigEndianByteOrder` in MIPS |
tree | commitdiff |
2020-09-09 |
Giacomo Travaglini | arch-arm: Fix ArmISA namespace requirement for TME... |
tree | commitdiff |
2020-09-09 |
Gabe Black | arch: Add a virtual destructor to BaseHTMCheckpoint. |
tree | commitdiff |
2020-09-08 |
Gabe Black | arm: Remove "using namespace ArmISA" from arch/arm... |
tree | commitdiff |
2020-09-08 |
Timothy Hayes | arch-arm: Transactional Memory Extension (TME) |
tree | commitdiff |
2020-09-08 |
Gabe Black | arm: Replicate the PageBytes constant in the ArmSystem... |
tree | commitdiff |
2020-09-08 |
Andreas Sandberg | base, sim: Make ByteOrder into a ScopedEnum accessible... |
tree | commitdiff |
next |