mem: Restructure whole-line writes to simplify write merging
[gem5.git] / src / arch /
2018-10-18 Gabe Blacknull: Stop specifying an endianness in isa_traits.hh.
2018-10-17 Gabe Blackarch: Include some additional headers in arch/generic...
2018-10-17 Gabe Blackarch: Get rid of the unused type AnyReg.
2018-10-12 Gabe Blackarch: Explicitly specify the endianness in the generic...
2018-10-12 Gabe Blackmips: Use little endian packet accessors.
2018-10-12 Gabe Blacksparc: Use big endian packet accessors.
2018-10-12 Gabe Blackx86: Use little endian packet accessors.
2018-10-12 Ciro Santillisyscall_emul: update arm uname release to 3.7.0+
2018-10-09 Giacomo Travagliniarch-arm: Add have_crypto System parameter
2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto AES
2018-10-09 Giacomo Travagliniarch-arm: AArch64 Crypto SHA
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto AES
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto SHA
2018-10-08 Ciro Santillidev, arm: remove the RealViewEB platform
2018-10-08 Matteo Andreozziarch-arm: Mark ArmProcess method as override
2018-10-02 Giacomo Travaglinisim-se: Set ArmProcess64 hwcaps depending on ID regs
2018-10-02 Giacomo Travaglinisim-se: Different HWCAP for ArmProcess32/64
2018-10-02 Edmund Grimley Evansarch-arm: Add FP16 support introduced by Armv8.2-A
2018-10-02 Gabor Dozsaarch: Fix unserialization of VectorReg value
2018-10-02 Edmund Grimley Evansarch-arm: Add FP16 support and other primitives to...
2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID regs as bitunions
2018-10-01 Giacomo Travagliniarch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
2018-10-01 Giacomo Travagliniarch-arm: Move MiscReg BitUnions into a separate header...
2018-10-01 Giacomo Travagliniarch-arm: Init AArch64 ID registers in SE mode
2018-09-28 Giacomo Travagliniarch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
2018-09-19 Brandon Pottersyscall_emul: implement dir-related syscalls
2018-09-19 Brandon Pottersyscall_emul: expand AuxVector class
2018-09-13 Earl OuFix SConstruct for asan build
2018-09-13 Anouk Van Laerarch-arm: Correction for address size in EL1&0 translation
2018-09-13 Anouk Van Laerarch-arm: Correction to address size in EL2/EL3
2018-09-12 Ciro Santillidev-arm: rename Pl390 to GicV2
2018-09-10 Giacomo Travaglinidev-arm: Factory SimObject for generating ArmInterruptPin
2018-09-10 Andreas Sandbergarm: Use the interrupt adaptor in the PMU
2018-09-10 Andreas Sandbergarm: Add support for tracking TCs in ISA devices
2018-08-21 Jason Lowe-Powermisc: Appease GCC 8
2018-08-10 Giacomo Gabrielliarm: Add support for RCpc load-acquire instructions...
2018-08-02 Andreas Sandbergarch-arm: Don't fail to initialise PMU if BP is missing
2018-07-28 Alec Roelkearch-riscv: Add xret instructions
2018-07-28 Alec Roelkearch-riscv: Add support for trap value register
2018-07-28 Alec Roelkearch-riscv: Add support for fault handling
2018-07-16 Giacomo Travagliniarch-arm: Introduce ARMv8.1 Virtual Timer System Registers
2018-07-16 Giacomo Travagliniarch-arm: Introduce RAS System Registers
2018-07-09 Robertarch-riscv: enable rudimentary fs simulation
2018-07-09 Austin Harrisarch-riscv: Fix the srlw and srliw instructions.
2018-06-28 Andreas Sandbergarch-arm: Fix incorrect t{0,1}sz field in TTBCR
2018-06-25 Matt Sinclairsyscall_emul: adding symlink system call
2018-06-25 Matt Sinclairsyscall_emul: adding link system call
2018-06-22 Giacomo Travagliniarch-arm: AArch32 execution triggering AArch64 SW Break
2018-06-22 Giacomo Travagliniarch-arm: BadMode checking if corresponding EL is imple...
2018-06-14 Tuan Taarch: support issuing Atomic Mem Operation (AMO) requests
2018-06-14 Giacomo Travagliniarch-arm: Adapting IllegalExecution fault for AArch32
2018-06-14 Giacomo Travagliniarch-arm: Add Illegal Execution flag to PCState
2018-06-14 Giacomo Travagliniarch-arm: Read APSR in User Mode
2018-06-13 Giacomo Travagliniarch-arm: Fix missing Request allocation
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2018-06-06 Andreas Sandbergarch-arm: Remove dead doingStage2 variable in PT walker
2018-06-06 Andreas Sandbergarch-arm: Perform stage 2 lookups using the EL2 state
2018-06-06 Andreas Sandbergarch-arm: Respect EL from translation type
2018-06-06 Andreas Sandbergarch-arm: Fix page size handling when merging stage...
2018-06-06 Andreas Sandbergdev, arm: Add support for HYP & secure timers
2018-06-06 Andreas Sandbergarch-arm: Adjust breakpoint EC depending on source...
2018-05-29 Giacomo Travagliniarch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL...
2018-05-29 Giacomo Travagliniarch-arm: Remove unusued MISCREG_A64_UNIMPL
2018-05-29 Giacomo Travagliniarch-arm: MPIDR.MT = 1 in a multithreaded system
2018-05-29 Giacomo Travagliniarch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation...
2018-05-29 Giacomo Travagliniarch-arm: Implement ARMv8.1 TTBR1_EL2 register
2018-05-29 Giacomo Travagliniarch-arm: Add E2H bit to HCR_EL2 System register
2018-05-24 Gabe Blackx86: Add op classes to the MediaOps.
2018-05-16 Andreas Sandbergarch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
2018-05-16 Andreas Sandbergarch-arm: Add support for semihosting STDIO redirection
2018-05-12 Alec Roelkearch-riscv: Update CSR implementations
2018-05-08 Matt Sinclairarch-x86, arch-power: fix calls to bits and insertBits
2018-05-08 Giacomo Travagliniarch-arm: Map ID_x_EL1 registers to AArch32 version
2018-05-03 Tony Gutierrezarch-x86: Enable fstatfs for x86_64
2018-05-02 Steve Reinhardtarch-x86: implement movntps/movntpd SSE insts
2018-05-02 Gabe Blackx86: Add a ld/st microop flag for marking an access...
2018-05-02 Tony Gutierrezarch-x86: Enable the umask system call
2018-04-27 Giacomo Travaglinisim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-19 Giacomo Travagliniarch-arm: Add ARMv8.1 TTBR1_EL2 register
2018-04-19 Giacomo Travagliniarch-arm: Fix Unknown Instruction disassemble
2018-04-19 Giacomo Travagliniarch-arm: Change disassemble when MSR to UNKNOWN register
2018-04-18 Chuan Zhuarch-arm: Fix masking in CPACR_EL1
2018-04-18 Chuan Zhuarch-arm: Mask out unsupported trapped exception handli...
2018-04-18 Chuan Zhuarch-arm: Fix FPEXC32_EL2 to FPEXC mapping
2018-04-18 Giacomo Travagliniarch-arm: Adding MiscReg Priv (EL1) global flag
2018-04-18 Chuan Zhuarch-arm: Correct masking of cp10 and cp11 in CPACR
2018-04-18 Giacomo Travagliniarch-arm: Using explicit invalidation in TLB
2018-04-17 Giacomo Travagliniarch-arm: Fix secure MiscReg access when EL3 is not...
2018-04-10 Giacomo Travagliniarch-arm: Fix mrc,mcr to cop14 disassemble
2018-04-06 Gabe Blackarch: alpha: Fix an 8 year old bug from the transition...
2018-04-06 Giacomo Travagliniarch-arm: Add support for Tarmac trace generation
2018-04-06 Giacomo Travagliniarch-arm: Add support for Tarmac trace-based simulation
2018-04-06 Giacomo Travagliniarch-arm: Fix AArch32 branch instructions disassemble
2018-04-06 Giacomo Travagliniarch-arm: Fix secure write of SCTLR when EL3 is AArch64
2018-04-06 Giacomo Travagliniarch-arm: Correct mcrr,mrrc disassemble
2018-03-27 Gabe Blackarch: cpu: Make the ExtMachInst type a template argumen...
2018-03-27 Gabe Blacksparc: Add some missing M5_FALLTHROUGHs and breaks.
2018-03-26 Gabe Blackarch: Fix all override related warnings.
2018-03-26 Gabe Blackarch: Add a virtual asBytes function to the StaticInst...
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