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v3d: Add support for CS workgroup/invocation id intrinsics.
[mesa.git]
/
src
/
broadcom
/
compiler
/
vir_register_allocate.c
2019-01-14
Eric Anholt
v3d: Add support for CS workgroup/invocation id intrinsics.
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2018-08-06
Eric Anholt
v3d: Avoid spilling that breaks the r5 usage after...
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2018-08-06
Eric Anholt
v3d: Wait for TMU writes to complete before continuing...
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2018-08-06
Eric Anholt
v3d: Add some debug code for forcing register spilling.
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2018-07-23
Eric Anholt
v3d: Switch to using the new SFU instructions on V3D...
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2018-07-23
Eric Anholt
v3d: Rotate through registers to improve post-RA schedu...
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2018-03-19
Eric Anholt
broadcom/vc5: Add support for register spilling.
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2018-01-13
Eric Anholt
broadcom/vc5: Use THRSW to enable multi-threaded shaders.
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2018-01-13
Eric Anholt
broadcom/vc5: Use a physical-reg-only register class...
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2018-01-13
Eric Anholt
broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D...
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2018-01-13
Eric Anholt
broadcom/vc5: Add support for V3Dv4 signal bits.
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2017-10-10
Eric Anholt
broadcom: Add VC5 NIR compiler.
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