| 2020-06-12 |
Gabe Black | arch,cpu: Add a setThreadContext method to the ISA... |
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| 2020-06-11 |
Gabe Black | arch,cpu: Change setCPU to setThreadContext in Interrupts. |
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| 2020-06-08 |
Bobby R. Bruce | misc: Merge hotfix v20.0.0.2 into develop |
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| 2020-06-02 |
Bobby R. Bruce | misc: Merge branch version update into develop |
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| 2020-06-02 |
Bobby R. Bruce | misc: Merge in 'hotfix-m5-tick-rounding-error' |
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| 2020-05-28 |
Bobby R. Bruce | Merge branch 'release-staging-v20.0.0.0' into develop |
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| 2020-05-28 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.0.0.0' into... |
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| 2020-05-19 |
Gabe Black | arch,base,cpu,sim: Statically allocate debugSymbolTable. |
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| 2020-05-19 |
Gabe Black | arch,base,cpu,kern,sim: Encapsulate symbols in a class. |
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| 2020-04-29 |
Anouk Van Laer | sim-power: Creation of PowerState class |
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| 2020-04-22 |
Gabe Black | base,arch,sim,cpu: Move object file loader components... |
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| 2020-03-07 |
Gabe Black | arch,cpu,gpu-compute,mem: Remove asid from Request... |
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| 2020-02-26 |
Bobby R. Bruce | misc: merge branch 'release-staging-v19.0.0.0' into... |
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| 2020-02-24 |
Bobby R. Bruce | misc: Merged release-staging-v19.0.0.0 into develop |
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| 2020-02-17 |
Gabe Black | cpu: Delete authors lists from the cpu directory. |
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| 2020-02-01 |
Gabe Black | sim,cpu: Move the call to initCPU into System. |
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| 2020-01-29 |
Ayaz Akram | cpu: move initCPU calls from initState to init |
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| 2020-01-23 |
Gabe Black | cpu: Consolidate and move the CPU's calls to TheISA... |
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| 2019-11-25 |
Ciro Santilli | cpu: log thread activate and suspend with --debug-flags... |
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| 2019-10-25 |
Gabe Black | cpu: Switch off of the CPU's comInstEventQueue. |
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| 2019-10-25 |
Gabe Black | cpu: Access inst events through ThreadContext instead... |
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| 2019-10-25 |
Gabe Black | cpu: Delegate comInstEventQueue methods to the ThreadCo... |
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| 2019-10-25 |
Gabe Black | cpu: Make accesses to comInstEventQueue indirect throug... |
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| 2019-10-17 |
Gabe Black | cpu: Get rid of load count based events. |
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| 2019-08-27 |
Gabe Black | cpu, dev, mem: Use the new Port methods. |
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| 2019-04-28 |
Gabe Black | mem: Minimize the use of MemObject. |
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| 2019-03-28 |
Javier Bueno | cpu: Added a probe to notify the address of retired... |
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| 2019-03-19 |
Gabe Black | arch, cpu, dev, gpu, mem, sim, python: start using... |
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| 2019-03-01 |
Andrea Mondelli | mem-cache: alias to mem::getMasterPort in TLB class |
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| 2019-02-08 |
Tuan Ta | cpu: support atomic memory request type with AtomicOpFu... |
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| 2018-06-21 |
Giacomo Travaglini | cpu: Fix bug introduced by RequestPtr type change |
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| 2018-06-11 |
Giacomo Travaglini | misc: Using smart pointers for memory Requests |
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| 2018-04-27 |
Giacomo Travaglini | sim,cpu,mem,arch: Introduced MasterInfo data structure |
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| 2017-12-22 |
Gabe Black | arch,cpu: "virtualize" the TLB interface. |
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| 2017-12-04 |
Gabe Black | misc: Rename misc.(hh|cc) to logging.(hh|cc) |
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| 2017-11-21 |
Jose Marinho | cpu, cpu, sim: move Cycle probe update |
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| 2017-11-20 |
Jose Marinho | cpu: Make automatic transition to OFF optional |
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| 2017-11-20 |
Anouk Van Laer | pwr: Adds logic to enter power gating for the cpu model |
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| 2017-07-12 |
Sean Wilson | cpu: Refactor some Event subclasses to lambdas |
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| 2017-07-12 |
Jose Marinho | cpu, sim: Add param to force CPUs to wait for GDB |
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| 2017-06-20 |
Sean Wilson | cpu, gpu-compute: Replace EventWrapper use with EventFu... |
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| 2015-07-20 |
Brandon Potter | syscall_emul: [patch 13/22] add system call retry capab... |
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| 2016-11-09 |
Brandon Potter | style: [patch 1/22] use /r/3648/ to reorganize includes |
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| 2016-06-06 |
David Guillen Fandos | pwr: Low-power idle power state for idle CPUs |
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| 2016-06-06 |
Stephan Diestelhorst | sim: Call regStats of base-class as well |
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| 2016-04-06 |
Andreas Sandberg | Revert power patch sets with unexpected interactions |
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| 2014-12-09 |
Akash Bagdia | power: Low-power idle power state for idle CPUs |
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| 2016-04-05 |
Geoffrey Blake | cpu: Query CPU for inst executed from Python |
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| 2015-11-27 |
Andreas Sandberg | base: Add support for changing output directories |
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| 2016-02-07 |
Steve Reinhardt | style: eliminate explicit boolean comparisons |
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| 2016-02-07 |
Steve Reinhardt | style: fix missing spaces in control statements |
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| 2015-11-20 |
Andreas Sandberg | cpu: Enforce 1 interrupt controller per thread |
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| 2015-09-30 |
Mitch Hayenga | isa,cpu: Add support for FS SMT Interrupts |
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| 2015-09-30 |
Mitch Hayenga | cpu: Add per-thread monitors |
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| 2015-09-30 |
Mitch Hayenga | cpu: Change thread assignments for heterogenous SMT |
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| 2015-08-21 |
Andreas Hansson | cpu: Move invldPid constant from Request to BaseCPU |
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| 2015-07-07 |
Andreas Sandberg | sim: Refactor the serialization base class |
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| 2015-04-14 |
Malek Musleh | config, cpu: fix progress interval for switched CPUs |
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| 2015-01-10 |
Nikos Nikoleris | cpu: fix RetiredStores probe point |
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| 2014-11-14 |
Andreas Hansson | arm: Fixes based on UBSan and static analysis |
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| 2014-11-06 |
Marc Orr | x86 isa: This patch attempts an implementation at mwait. |
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| 2014-10-16 |
Andreas Sandberg | cpu: Probe points for basic PMU stats |
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| 2014-05-09 |
Geoffrey Blake | arch, arm: Preserve TLB bootUncacheability when switchi... |
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| 2014-05-09 |
Akash Bagdia | cpu, arm: Allow the specification of a socket field |
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| 2013-11-25 |
Steve Reinhardt... | sim: simulate with multiple threads and event queues |
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| 2013-07-18 |
Andreas Hansson | mem: Set the cache line size on a system level |
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| 2013-06-11 |
Andreas Sandberg | cpu: Add support for scheduling multiple inst/load... |
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| 2013-04-22 |
Dam Sunwoo | cpu: generate SimPoint basic block vector profiles |
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| 2013-03-26 |
Andreas Hansson | cpu: Remove CpuPort and use MasterPort in the CPU classes |
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| 2013-02-15 |
Andreas Sandberg | cpu: Refactor memory system checks |
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| 2013-01-07 |
Andreas Sandberg | cpu: Unify the serialization code for all of the CPU... |
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| 2013-01-07 |
Andreas Sandberg | cpu: Flush TLBs on switchOut() |
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| 2013-01-07 |
Andreas Sandberg | cpu: Rename defer_registration->switched_out |
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| 2013-01-07 |
Andreas Sandberg | cpu: Introduce sanity checks when switching between... |
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| 2013-01-07 |
Andreas Sandberg | arch: Make the ISA class inherit from SimObject |
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| 2012-11-02 |
Dam Sunwoo | ARM: dump stats and process info on context switches |
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| 2012-10-15 |
Andreas Hansson | Port: Add protocol-agnostic ports in the port hierarchy |
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| 2012-09-13 |
Joel Hestness | Base CPU: Initialize profileEvent to NULL |
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| 2012-08-28 |
Andreas Hansson | Clock: Rework clocks to avoid tick-to-cycle transformations |
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| 2012-08-28 |
Andreas Hansson | Port: Stricter port bind/unbind semantics |
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| 2012-08-21 |
Andreas Hansson | Clock: Move the clock and related functions to ClockedO... |
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| 2012-08-15 |
Anthony Gutierrez | O3,ARM: fix some problems with drain/switchout function... |
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| 2012-07-09 |
Andreas Hansson | Fix: Address a few benign memory leaks |
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| 2012-05-01 |
Andreas Hansson | MEM: Separate requests and responses for timing accesses |
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| 2012-04-14 |
Andreas Hansson | MEM: Separate snoops and normal memory requests/responses |
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| 2012-03-30 |
William Wang | MEM: Introduce the master/slave port sub-classes in C++ |
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| 2012-03-09 |
Geoffrey Blake | CheckerCPU: Make CheckerCPU runtime selectable instead... |
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| 2012-03-02 |
Andreas Hansson | CPU: Check that the interrupt controller is created... |
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| 2012-02-24 |
Andreas Hansson | CPU: Round-two unifying instr/data CPU ports across... |
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| 2012-02-12 |
Anthony Gutierrez | cpu: add separate stats for insts/ops both globally... |
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| 2012-02-12 |
Ali Saidi | mem: Add a master ID to each request object. |
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| 2012-02-01 |
Gabe Black | Merge ... head, hopefully the last time for this batch. |
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| 2012-01-31 |
Koan-Sin Tan | clang: Enable compiling gem5 using clang 2.9 and 3.0 |
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| 2012-01-31 |
Geoffrey Blake | CheckerCPU: Re-factor CheckerCPU to be compatible with... |
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| 2012-01-31 |
Gabe Black | Merge with main repository. |
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| 2012-01-29 |
Gabe Black | Yet another merge with the main repository. |
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| 2012-01-28 |
Gabe Black | Merge with the main repo. |
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| 2012-01-16 |
Gabe Black | Merge yet again with the main repository. |
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| 2012-01-17 |
Andreas Hansson | MEM: Separate queries for snooping and address ranges |
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| 2012-01-17 |
Andreas Hansson | CPU: Moving towards a more general port across CPU... |
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