2019-03-14 |
Andrea Mondelli | cpu: Refactor of Physical Register implementation |
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2019-02-08 |
Tuan Ta | cpu: support atomic memory request type with AtomicOpFu... |
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2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
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2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
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2019-01-24 |
Rekai Gonzalez-Alb... | cpu-o3: O3 LSQ Generalisation |
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2019-01-16 |
Gabe Black | cpu: dev: sim: gpu-compute: Banish some ISA specific... |
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2018-12-20 |
Gabe Black | arch, cpu: Remove float type accessors. |
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2018-11-16 |
Rekai Gonzalez-Alb... | cpu: Fix the usage of const DynInstPtr |
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2018-06-14 |
Tuan Ta | cpu: add a new instruction type 'Atomic' |
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2018-06-11 |
Giacomo Travaglini | misc: Using smart pointers for memory Requests |
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2018-06-11 |
Giacomo Travaglini | misc: Substitute pointer to Request with aliased RequestPtr |
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2018-01-09 |
Gabe Black | cpu: Add a NotAnInst flag to the BaseDynInst class. |
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2018-01-09 |
Gabe Black | cpu, power: Get rid of the remnants of the EA computati... |
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2017-07-05 |
Rekai Gonzalez-Alb... | arch: ISA parser additions of vector registers |
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2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Added interface for vector reg file |
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2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Result refactoring |
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2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Simplify the rename interface and use RegId |
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2017-07-05 |
Nathanael Premillieu | cpu: Physical register structural + flat indexing |
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2017-07-05 |
Nathanael Premillieu | arch, cpu: Architectural Register structural indexing |
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2016-08-15 |
Nikos Nikoleris | cpu, arch: fix the type used for the request flags |
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2016-04-07 |
Mitch Hayenga | mem: Remove threadId from memory request class |
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2016-04-06 |
Andreas Sandberg | Revert power patch sets with unexpected interactions |
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2016-04-05 |
Mitch Hayenga | mem: Remove threadId from memory request class |
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2016-01-18 |
Steve Reinhardt | cpu. arch: add initiateMemRead() to ExecContext interface |
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2016-01-18 |
Steve Reinhardt | cpu: remove unnecessary data ptr from O3 internal read... |
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2016-01-11 |
Andreas Hansson | scons: Enable -Wextra by default |
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2015-09-30 |
Mitch Hayenga | cpu: Add per-thread monitors |
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2015-09-15 |
Hongil Yoon | cpu, o3: consider split requests for LSQ checksnoop... |
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2015-08-07 |
Andreas Sandberg | base: Declare a type for context IDs |
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2015-07-28 |
Nilay Vaish | revert 5af8f40d8f2c |
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2015-07-26 |
Nilay Vaish | cpu: implements vector registers |
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2015-05-15 |
Andreas Hansson | misc: Appease gcc 5.1 |
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2015-05-05 |
Andreas Sandberg | mem, cpu: Add a separate flag for strictly ordered... |
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2015-03-02 |
Rekai | cpu: o3 register renaming request handling improved |
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2015-02-11 |
Andreas Sandberg | sim: Move the BaseTLB to src/arch/generic/ |
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2015-01-25 |
Ali Saidi | sim: Clean up InstRecord |
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2014-11-06 |
Marc Orr | x86 isa: This patch attempts an implementation at mwait. |
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2014-10-16 |
Andreas Hansson | arch: Use shared_ptr for all Faults |
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2014-09-27 |
Andreas Hansson | arch: Use const StaticInstPtr references where possible |
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2014-09-03 |
Andreas Sandberg | arch, cpu: Factor out the ExecContext into a proper... |
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2014-05-09 |
Akash Bagdia | cpu, arm: Allow the specification of a socket field |
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2014-03-07 |
Andreas Hansson | cpu: Make CPU and ThreadContext getters const |
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2014-01-24 |
Ali Saidi | cpu: Add CPU support for generatig wake up events when... |
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2014-01-24 |
Dam Sunwoo | mem: per-thread cache occupancy and per-block ages |
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2013-10-17 |
Ali Saidi | cpu: Fix O3 uncacheable load that is replayed but misse... |
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2013-10-15 |
Yasuko Eckert | cpu: add a condition-code register class |
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2013-07-18 |
Andreas Hansson | mem: Set the cache line size on a system level |
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2012-06-05 |
Ali Saidi | O3: Clean up the O3 structures and try to pack them... |
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2012-06-05 |
Ali Saidi | sim: Remove FastAlloc |
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2012-03-19 |
Andreas Hansson | gcc: Clean-up of non-C++0x compliant code, first steps |
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2012-03-09 |
Geoffrey Blake | CheckerCPU: Make CheckerCPU runtime selectable instead... |
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2012-02-24 |
Andreas Hansson | CPU: Round-two unifying instr/data CPU ports across... |
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2012-02-12 |
Ali Saidi | mem: Add a master ID to each request object. |
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2012-02-07 |
Gabe Black | Faults: Turn off arch/faults.hh |
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2012-02-01 |
Gabe Black | Merge ... head, hopefully the last time for this batch. |
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2012-01-31 |
Geoffrey Blake | CheckerCPU: Re-factor CheckerCPU to be compatible with... |
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2012-01-31 |
Gabe Black | Merge with main repository. |
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2012-01-29 |
Gabe Black | Yet another merge with the main repository. |
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2012-01-28 |
Gabe Black | Merge with the main repo. |
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2012-01-16 |
Gabe Black | Merge yet again with the main repository. |
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2012-01-07 |
Gabe Black | Another merge with the main repository. |
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2012-01-07 |
Gabe Black | Merge with the main repository again. |
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2012-01-07 |
Gabe Black | Merge with main repository. |
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2011-11-18 |
Gabe Black | SE/FS: Get rid of includes of config/full_system.hh. |
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2011-09-13 |
Ali Saidi | LSQ: Only trigger a memory violation with a load/load... |
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2011-09-09 |
Gabe Black | StaticInst: Merge StaticInst and StaticInstBase. |
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2011-08-14 |
Gabe Black | O3: Add a pointer to the macroop for a microop in the... |
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2011-08-07 |
Gabe Black | Translation: Use a pointer type as the template argument. |
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2011-08-02 |
Gabe Black | O3: Get rid of the raw ExtMachInst constructor on DynInsts. |
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2011-07-03 |
Nilay Vaish | Merged with Gabe's recent changes. |
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2011-07-03 |
Gabe Black | ExecContext: Rename the readBytes/writeBytes functions... |
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2011-07-03 |
Gabe Black | ExecContext: Get rid of the now unused read/write templ... |
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2011-04-04 |
Ali Saidi | CPU: Remove references to memory copy operations |
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2011-04-04 |
Ali Saidi | O3: Tighten memory order violation checking to 16 bytes. |
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2011-02-22 |
Brad Beckmann | m5: merged in hammer fix |
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2011-02-16 |
Nathan Binkert | merge alpha system files into tree |
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2011-02-12 |
Giacomo Gabrielli | O3: Enhance data address translation by supporting... |
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2010-12-08 |
Ali Saidi | O3: Support squashing all state after special instruction |
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2010-12-08 |
Giacomo Gabrielli | O3: Make all instructions that write a misc. register... |
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2010-11-08 |
Ali Saidi | ARM/Alpha/Cpu: Change prefetchs to be more like normal... |
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2010-10-31 |
Gabe Black | ISA,CPU,etc: Create an ISA defined PC type that abstrac... |
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2010-09-14 |
Gabe Black | Faults: Pass the StaticInst involved, if any, to a... |
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2010-08-23 |
Min Kyu Jeong | CPU: Make Exec trace to print predication result (if... |
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2010-08-23 |
Min Kyu Jeong | ARM/O3: store the result of the predicate evaluation... |
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2010-08-23 |
Ali Saidi | CPU: Set a default value when readBytes faults. |
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2010-08-13 |
Gabe Black | Merge with head. |
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2010-08-13 |
Gabe Black | CPU: Add readBytes and writeBytes functions to the... |
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2010-02-20 |
Timothy M. Jones | BaseDynInst: Preserve the faults returned from read... |
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2010-02-12 |
Timothy M. Jones | O3PCU: Split loads and stores that cross cache line... |
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2010-02-12 |
Timothy M. Jones | BaseDynInst: Make the TLB translation timing instead... |
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2010-01-19 |
Derek Hower | merge |
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2009-09-23 |
Nathan Binkert | arch: nuke arch/isa_specific.hh and move stuff to gener... |
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2009-08-03 |
Derek Hower | Automated merge with ssh://hg@m5sim.org/m5 |
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2009-08-02 |
Steve Reinhardt | Fix setting of INST_FETCH flag for O3 CPU. |
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2009-05-26 |
Nathan Binkert | types: add a type for thread IDs and try to use it... |
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2009-04-09 |
Nathan Binkert | tlb: More fixing of unified TLB |
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2009-04-06 |
Gabe Black | Merge ARM into the head. ARM will compile but may not... |
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2009-02-25 |
Gabe Black | ISA: Replace the translate functions in the TLBs with... |
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2009-02-25 |
Gabe Black | CPU: Get rid of translate... functions from various... |
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2008-11-10 |
Clint Smullen | O3CPU: Make the instcount debugging stuff per-cpu. |
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