misc: Replaced master/slave terminology
[gem5.git] / src / cpu / minor / lsq.cc
2020-09-10 Shivani Parekhmisc: Replaced master/slave terminology
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-08 Bobby R. Brucemisc: Merge hotfix v20.0.0.2 into develop
2020-06-02 Bobby R. Brucemisc: Merge branch version update into develop
2020-06-02 Bobby R. Brucemisc: Merge in 'hotfix-m5-tick-rounding-error'
2020-05-28 Bobby R. BruceMerge branch 'release-staging-v20.0.0.0' into develop
2020-05-28 Bobby R. Brucemisc: Merge branch 'release-staging-v20.0.0.0' into...
2020-05-19 Tiago Mückcpu-minor: fix store-release issuing
2020-03-07 Gabe Blackarch,cpu,gpu-compute,mem: Remove asid from Request...
2020-03-04 Gabe Blackarch,cpu,mem: Replace the mmmapped IPR mechanism with...
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2020-01-03 Gabor Dozsacpu: Disable MinorCPU value forwarding with write strobes
2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
2019-09-23 Jordi Vaquerocpu, mem: Changing AtomicOpFunctor* for unique_ptr...
2019-07-27 Gabor Dozsacpu: Add first-/non-faulting load support to Minor...
2019-05-11 Giacomo Gabriellicpu,mem: Add support for partial loads/stores and wide...
2019-02-08 Tuan Tacpu: support atomic memory request type with AtomicOpFu...
2018-11-27 Gabe Blackarch, base, cpu, gpu, mem: Replace assert(0 or false...
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2017-12-05 Nikos Nikoleriscpu: Add support for CMOs in the cpu models
2017-09-01 Pau Cabrecpu-minor: Fix for addr range coverage calculation
2017-07-12 Sean Wilsoncpu: Refactor some Event subclasses to lambdas
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-08-15 Nikos Nikoleriscpu, arch: fix the type used for the request flags
2016-07-21 Mitch Hayengacpu: Add SMT support to MinorCPU
2016-04-07 Mitch Hayengamem: Remove threadId from memory request class
2016-04-06 Andreas SandbergRevert power patch sets with unexpected interactions
2016-04-05 Mitch Hayengamem: Remove threadId from memory request class
2015-07-19 Krishnendra Nathellacpu: Fix LLSC atomic CPU wakeup
2015-09-30 Mitch Hayengacpu: Add per-thread monitors
2015-08-21 Andreas Hanssonmem: Reflect that packet address and size are always...
2015-05-05 Andreas Sandbergmem, cpu: Add a separate flag for strictly ordered...
2015-02-11 Steve Reinhardtmem: restructure Packet cmd initialization a bit more
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-01-25 Ali Saidisim: Clean up InstRecord
2015-01-20 Andreas Hanssoncpu: Fix retry bug in MinorCPU LSQ
2015-01-03 Andrew Lukefahrminor: fixed LSQ MasterPortID
2014-12-02 Andrew Bardsleycpu: Fix retries on barrier/store in Minor's store...
2014-12-02 Andreas Hanssonmem: Assume all dynamic packet data is array allocated
2014-12-02 Andreas Hanssonmem: Add const getters for write packet data
2014-10-30 Ali Saidiautomated merge
2014-10-30 Andrew Bardsleycpu: Fix barrier push to store buffer when full bug...
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible
2014-09-12 Andrew Bardsleycpu: Fix memory access in Minor not setting parent...
2014-07-23 Andrew Bardsleycpu: `Minor' in-order CPU model