cpu: Delete authors lists from the cpu directory.
[gem5.git] / src / cpu / o3 / lsq_unit_impl.hh
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2019-10-30 Giacomo Gabriellicpu-o3: Fix handling of some mem. order violations
2019-07-28 Gabor Dozsacpu-o3: Fix too strict assert condition in writeback()
2019-07-27 Gabor Dozsacpu: Add first-/non-faulting load support to Minor...
2019-05-11 Giacomo Gabriellicpu,mem: Add support for partial loads/stores and wide...
2019-05-11 Giacomo Gabriellicpu: Add a memory access predicate
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs
2019-02-27 Andrea Mondellimisc: Segmentation Fault during O3PipeView execution
2019-02-22 Gabor Dozsacpu-o3: Add cache read ports limit to LSQ
2019-02-08 Tuan Tacpu: support atomic memory request type with AtomicOpFu...
2019-01-24 Rekai Gonzalez-Alb... cpu-o3: O3 LSQ Generalisation
2018-12-11 Tony Gutierrezcpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor
2018-12-03 Rekai Gonzalez-Alb... cpu: Change raw pointers to STL Containers
2018-11-16 Rekai Gonzalez-Alb... cpu: Fix the usage of const DynInstPtr
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2017-10-13 Nikos Nikoleriscpu-o3: Check predication before the SQ size for a...
2017-10-13 Nikos Nikoleriscpu-o3: Avoid early checker verification for store...
2016-12-21 Arthur Peraiscpu: Clarify meaning of cachePorts variable in lsq_unit...
2015-08-10 Stephan Diestelhorstmem, cpu: Add assertions to snoop invalidation logic
2015-07-19 Krishnendra Nathellacpu: Fix LLSC atomic CPU wakeup
2015-12-04 Pau Cabrecpu: fix unitialized variable which may cause assertion...
2015-09-15 Hongil Yooncpu, o3: consider split requests for LSQ checksnoop...
2015-05-05 Andreas Sandbergmem, cpu: Add a separate flag for strictly ordered...
2014-12-02 Marco Elvercpu, o3: Ignored invalidate causing same-address load...
2014-12-02 Stephan Diestelhorstcpu: Move packet deallocation to recvTimingResp in...
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
2014-09-20 Andreas Hanssonbase: Clean up redundant string functions and use C++11
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types
2014-09-03 Mitch Hayengacpu: Fix cache blocked load behavior in o3 cpu
2014-09-03 Mitch Hayengacpu: Change writeback modeling for outstanding instructions
2014-06-21 Binh Phamo3: split load & store queue full cases in rename
2014-06-01 Steve Reinhardtstyle: eliminate equality tests with true and false stable_2014_08_26
2014-04-01 Mitch Hayengacpu: Fix case where o3 lsq could print out uninitialize...
2014-03-25 Marco Elvercpu: o3: lsq: Fix TSO implementation
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines.
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Matt Horsnellbase: add support for probe points and common probes
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths...
2013-10-17 Matt Horsnellcpu: add consistent guarding to *_impl.hh files.
2013-10-17 Faissal Sleimancpu: Put in assertions to check for maximum supported...
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-02-15 Matt Horsnello3: fix tick used for renaming and issue with range...
2013-01-07 Andreas Sandbergcpu: Rewrite O3 draining to avoid stopping in microcode
2013-01-07 Andreas Sandbergcpu: Fix O3 LSQ debug dumping constness and formatting
2013-01-07 Ali Saidio3: Fix issue with LLSC ordering and speculation
2012-12-06 Nathanael Premillieuo3 cpu: remove some unused buggy functions in the lsq
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Nilay VaishO3 CPU LSQ: Implement TSO
2011-09-27 Gabe BlackO3: Tidy up some DPRINTFs in the LSQ.
2011-09-27 Gabe BlackFaults: Replace calls to genMachineCheckFault with...
2011-09-26 Nilay VaishLSQ: Moved a couple of lines to enable O3 + Ruby
2011-09-23 Steve Reinhardtevent: minor cleanup
2011-09-13 Ali SaidiLSQ: Only trigger a memory violation with a load/load...
2011-08-01 Gabe BlackO3: Implement memory mapped IPRs for O3.
2011-05-05 Ali SaidiO3: Fix a small corner case with the lsq hazard detecti...
2011-04-21 Nathan Binkertstats: one more name violation
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-04-04 Ali SaidiO3: Tighten memory order violation checking to 16 bytes.
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiO3: Fix unaligned stores when cache blocked
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2011-01-18 Matt HorsnellO3: Fix corner cases where multiple squashes/fetch...
2011-01-18 Ali SaidiARM: Add support for moving predicated false dest opera...
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-12-08 Min Kyu JeongO3: Support SWAP and predicated loads/store in ARM.
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-08-23 Min Kyu JeongO3: Skipping mem-order violation check for uncachable...
2010-08-23 Min Kyu JeongCPU: Make Exec trace to print predication result (if...
2010-08-23 Min Kyu JeongO3: Handle loads when the destination is the PC.
2010-08-23 Min Kyu JeongARM/O3: store the result of the predicate evaluation...
2010-02-12 Timothy M. JonesO3PCU: Split loads and stores that cross cache line...
2010-01-19 Derek Howermerge
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
2009-04-19 Gabe BlackMemory: Rename LOCKED for load locked store conditional...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2008-10-09 Nathan Binkerteventq: convert all usage of events to use the new...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-06 Stephen HinesMake the Event::description() a const function
2007-08-27 Gabe BlackMerge with head
2007-08-24 Ali SaidiMem: Make errors in the memory system be responses...
2007-08-21 Gabe BlackMerge with head.
2007-08-21 Kevin Limo3: Fix for retry ID bug.
2007-08-05 Gabe BlackMerge with head.
2007-08-03 Steve Reinhardtmerge from head
2007-08-01 Nathan Binkertmerge: mips fix to getArgument
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