misc: Merge branch v20.1.0.3 hotfix into develop
[gem5.git] / src / cpu / simple / timing.cc
2021-02-03 Bobby R. Brucemisc: Merge branch v20.1.0.3 hotfix into develop
2021-01-27 Gabe Blackbase,cpu,sim: Stop "using namespace TheISA".
2021-01-23 Gabe Blackcpu: Stop "using namespace std"
2020-12-03 Giacomo Travaglinicpu, sim: Remove unused System::totalNumInst
2020-11-26 Bobby R. BruceMerge "misc: Merge branch hotfix v20.1.0.2 branch into...
2020-11-19 Hoa Nguyencpu,stats: Update stats style for base.hh and base.cc
2020-11-19 Hoa Nguyencpu-simple,stats: Update stats style
2020-11-16 Bobby R. Brucemisc: Merge branch hotfix v20.1.0.2 branch into develop
2020-10-30 Gabe Blackmisc: Delete the now unnecessary create methods.
2020-10-21 Giacomo Travaglinimisc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects.
2020-10-01 Bobby R. Brucemisc: Merge branch 'release-staging-v20.1.0.0' into...
2020-09-30 Giacomo Travaglinicpu: Never use a empty byteEnable
2020-09-28 Gabe Blackmisc: Update attribute syntax, and reorganize compiler.hh.
2020-09-10 Shivani Parekhmisc: Replaced master/slave terminology
2020-09-10 Bobby R. Brucecpu: Fixed unused var error when with fast builds
2020-09-08 Timothy Hayescpu: HTM Implementation for TimingCPU
2020-09-07 Timothy Hayescpu: Add HTM CPU API
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-22 Michiel W. van Tolcpu: Use new InstRecord faulting flag in cpu models
2020-03-07 Gabe Blackarch,cpu,gpu-compute,mem: Remove asid from Request...
2020-03-04 Gabe Blackarch,cpu,mem: Replace the mmmapped IPR mechanism with...
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
2019-09-23 Jordi Vaquerocpu, mem: Changing AtomicOpFunctor* for unique_ptr...
2019-07-16 Giacomo Travaglinicpu: isDrained renamed to isCpuDrained
2019-05-11 Giacomo Gabriellicpu,mem: Add support for partial loads/stores and wide...
2019-02-08 Tuan Tacpu: support atomic memory request type with AtomicOpFu...
2018-06-14 Tuan Tacpu: Prevent suspended TimingSimple CPUs from fetching...
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2017-12-13 Gabe Blackarm,sparc,x86,base,cpu,sim: Replace the Twin(32|64...
2017-12-05 Nikos Nikoleriscpu: Add support for CMOs in the cpu models
2017-11-21 Jose Marinhocpu, cpu, sim: move Cycle probe update
2017-11-20 Anouk Van Laerpwr: Adds logic to enter power gating for the cpu model
2017-06-20 Sean Wilsoncpu, gpu-compute: Replace EventWrapper use with EventFu...
2015-07-20 Brandon Pottersyscall_emul: [patch 13/22] add system call retry capab...
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-08-15 Nikos Nikoleriscpu, arch: fix the type used for the request flags
2016-06-06 David Guillen Fandospwr: Low-power idle power state for idle CPUs
2016-04-07 Mitch Hayengamem: Remove threadId from memory request class
2016-04-06 Andreas SandbergRevert power patch sets with unexpected interactions
2016-04-05 Mitch Hayengamem: Remove threadId from memory request class
2014-12-09 Akash Bagdiapower: Low-power idle power state for idle CPUs
2015-07-19 Krishnendra Nathellacpu: Fix LLSC atomic CPU wakeup
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements
2016-02-07 Steve Reinhardtstyle: remove trailing whitespace
2016-01-18 Steve Reinhardtcpu. arch: add initiateMemRead() to ExecContext interface
2015-09-30 Mitch Hayengacpu,isa,mem: Add per-thread wakeup logic
2015-09-30 Mitch Hayengacpu: Add per-thread monitors
2015-09-30 Mitch Hayengaconfig,cpu: Add SMT support to Atomic and Timing CPUs
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API
2015-04-03 Nikos Nikoleriscpu: fix system total instructions accounting
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-02-03 Andreas Hanssoncpu: Ensure timing CPU sinks response before sending...
2015-01-25 Ali Saidisim: Clean up InstRecord
2015-01-22 Andreas Hanssonmem: Clean up Request initialisation
2014-12-05 Gabe Blackcpu: Only check for PC events on instruction boundaries.
2014-12-02 Andreas Hanssonmem: Assume all dynamic packet data is array allocated
2014-11-12 Ali Saidiarm: Fix timing wakeup with LLSC
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait.
2014-10-16 Andreas Sandbergcpu: Probe points for basic PMU stats
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate...
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines.
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths...
2013-08-19 Lena Olsoncpu: Accurately count idle cycles for simple cpu
2013-08-19 Andreas Hanssoncpu: Fix timing CPU drain check
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-04-22 Dam Sunwoosim: separate nextCycle() and clockEdge() in clockedObjects
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergcpu: Refactor memory system checks
2013-01-07 Andreas Sandbergcpu: Unify the serialization code for all of the CPU...
2013-01-07 Andreas Sandbergcpu: Make sure that a drained timing CPU isn't executin...
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out
2013-01-07 Andreas Sandbergcpu: Correctly call parent on switchOut() and takeOverF...
2013-01-07 Andreas Sandbergcpu: Check that the memory system is in the correct...
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are...
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
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