misc: Delete the now unnecessary create methods.
[gem5.git] / src / cpu / testers / traffic_gen / traffic_gen.cc
2020-10-30 Gabe Blackmisc: Delete the now unnecessary create methods.
2020-10-14 Gabe Blackmisc: Standardize the way create() constructs SimObjects.
2020-09-08 Wendy Elsassermem: Add NVM interface
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2019-09-30 Nikos Nikoleriscpu: Make use of DRAMCtrl::AddrMap in the traffic gener...
2018-07-13 Andreas Sandbergcpu: Unify error handling for address generators
2018-07-13 Andreas Sandbergcpu: Split the traffic generator into two classes
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-04-27 Giacomo Travaglinisim,cpu,mem,arch: Introduced MasterInfo data structure
2017-12-19 Riken Gohilcpu-tester: Added ExitGen to TrafficGen
2017-06-20 Sean Wilsoncpu, gpu-compute: Replace EventWrapper use with EventFu...
2016-06-20 Andreas Sandbergmem: Resolve TrafficGen trace relative to the config
2016-06-06 Stephan Diestelhorstsim: Call regStats of base-class as well
2016-05-26 Andreas Hanssoncpu: Add a basic progress check to the TrafficGen
2016-03-20 Andreas Hanssoncpu: warn if TrafficGen is suppressing a large numer...
2015-11-22 Andreas Hanssoncpu: Fix memory leak in traffic generator
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-03-19 Wendy Elsassercpu: Fix TrafficGen message format
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2014-09-20 Wendy Elsassercpu: Update DRAM traffic gen
2014-09-09 Andreas Hanssonmisc: Fix a number of unitialised variables and members
2014-09-03 Andreas Hanssonbase: Use the global Mersenne twister throughout
2014-08-10 Andreas Hanssoncpu: Ensure the traffic generator suppresses non-memory...
2014-03-23 Neha Agarwalcpu: DRAM Traffic Generator
2014-03-23 Stan Czerniawskicpu: Add basic check to TrafficGen initial state
2014-01-30 Xiangyu Dongcpu: fix bug when TrafficGen deschedules event
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-05-30 Sascha Bischoffcpu: Check that minimum TrafficGen period is less than...
2013-05-30 Sascha Bischoffcpu: Fix bug when reading in TrafficGen state transitions
2013-05-30 Andreas Hanssoncpu: Add request elasticity to the traffic generator
2013-05-30 Andreas Hanssoncpu: Block traffic generator when requests have to...
2013-05-30 Andreas Hanssoncpu: Move traffic generator sending out of generator...
2013-05-30 Andreas Hanssoncpu: Fold together the StateGraph and the TrafficGen
2013-04-22 Andreas Hanssoncpu: Make the generators usable outside the TrafficGen...
2013-03-12 Andreas Sandbergcpu: Fix state transition bug in the traffic generator
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-01-07 Andreas Hanssoncpu: Share the send functionality between traffic gener...
2013-01-07 Andreas Hanssoncpu: Add support for protobuf input for the trace generator
2013-01-07 Andreas Hanssoncpu: Encapsulate traffic generator input in a stream
2013-01-07 Andreas Hanssoncpu: Fix the traffic gen read percentage
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-09-21 Andreas HanssonTrafficGen: Add a basic traffic generator