cpu: make ExecSymbol show the symbol in addition to address
[gem5.git] / src / cpu / thread_context.cc
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop
2020-06-24 Gabe Blackfastmodel,cpu,sim: Eliminate EndQuiesceEvent and plumbing.
2020-06-24 Gabe Blacksim: Move guts of quiesce and quiesceTick from ThreadCo...
2020-06-17 Gabe Blackarch,cpu,sim: Eliminate the now empty kernel statistics...
2020-06-17 Gabe Blackarch,kern,sim: Move the stats in Kernel::Statistics...
2020-06-08 Bobby R. Brucemisc: Merge hotfix v20.0.0.2 into develop
2020-06-02 Bobby R. Brucemisc: Merge branch version update into develop
2020-06-02 Bobby R. Brucemisc: Merge in 'hotfix-m5-tick-rounding-error'
2020-05-28 Bobby R. BruceMerge branch 'release-staging-v20.0.0.0' into develop
2020-05-28 Bobby R. Brucemisc: Merge branch 'release-staging-v20.0.0.0' into...
2020-05-23 Gabe Blackcpu: Remove the ancient do_quiesce config option.
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into...
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop
2020-02-17 Gabe Blackcpu: Delete authors lists from the cpu directory.
2019-11-26 Gabe Blackarch,cpu: Get rid of ISA_HAS_CC_REGS and its associated...
2019-10-25 Gabe Blackcpu: Switch off of the CPU's comInstEventQueue.
2019-10-25 Gabe Blackcpu: Delegate comInstEventQueue methods to the ThreadCo...
2019-04-30 Gabe Blackarch: cpu: Track kernel stats using the base ISA agnost...
2019-04-22 Gabe Blackcpu: Eliminate the ProxyThreadContext class.
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal.
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific...
2017-12-04 Gabe Blackmisc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-09-14 Michael LeBeanesim: Refactor quiesce and remove FS asserts
2015-08-07 Andreas Sandbergbase: Declare a type for context IDs
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-01-07 Andreas Sandbergcpu: Fix broken thread context handover
2013-01-07 Andreas Sandbergcpu: Unify SimpleCPU and O3 CPU serialization code
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-10-31 Gabe BlackSE/FS: Make the functions available from the TC consist...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-01-19 Derek Howermerge
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2007-11-08 Ali SaidiCPU: Add function to explictly compare thread contexts...