mem-cache: Add match functions to QueueEntry
[gem5.git] / src / cpu /
2019-04-10 Giacomo Travaglinicpu: O3 switchFreeList checking VecElems instead of...
2019-04-05 Nikos Nikoleriscpu: Correctly account for executed instructions in...
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs
2019-04-03 Andrea Mondelliarch-mips: added missing override specifier (o3)
2019-03-28 Javier Buenocpu: Added a probe to notify the address of retired...
2019-03-27 Pau Cabrecpu: Fixed the indirect branch predictor GHR handling
2019-03-23 Andrea Mondellimisc: missing override specifier
2019-03-21 Ryan Gambordcpu-kvm: Added informative error message
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using...
2019-03-14 Andrea Mondellicpu: Refactor of Physical Register implementation
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE
2019-03-01 Andrea Mondellimem-cache: alias to mem::getMasterPort in TLB class
2019-02-27 Andrea Mondellimisc: Segmentation Fault during O3PipeView execution
2019-02-26 Srikant Bharadwajcpu: Fix indirect branch history updates
2019-02-22 Andreas Sandbergpython: Fix param -> int conversion issues
2019-02-22 Gabor Dozsacpu-o3: Add cache read ports limit to LSQ
2019-02-22 Andreas Sandbergpython: Make iterator handling Python 3 compatible
2019-02-19 Giacomo Gabriellicpu: Add ISA* getter in Thread interface
2019-02-15 Giacomo Travaglinicpu: Fix fast build broken due to unused variable
2019-02-13 Javier Buenocpu: Added 8KB and 64KB TAGE-SC-L branch predictor
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global...
2019-02-08 Jairo Balartcpu: Proposal for changing the indirect branch predicto...
2019-02-08 Tuan Tacpu: support atomic memory request type with AtomicOpFu...
2019-02-08 Tuan Tacpu: fix how branching is handled when a thread is...
2019-02-08 Tuan Tacpu: stop scheduling suspended threads in all stages...
2019-02-08 Tuan Tasim,cpu: make exit_group halt all threads in a group
2019-02-08 Tuan Tacpu: fixed how O3 CPU executes an exit system call
2019-02-06 Tuan Tacpu: fix how a thread starts up in MinorCPU
2019-02-05 Andrea Mondellimisc: added missing override specifier
2019-02-05 Javier Buenocpu: Made the Loop Predictor a SimObject
2019-02-05 Jairo Balartcpu: Made TAGE a SimObject that can be used by other...
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal.
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
2019-01-25 Giacomo Travaglinicpu: O3 rename using the flatIndex instead of index
2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
2019-01-25 Giacomo Travaglinicpu: Add VecElem entries in MinorCPU Scoreboard
2019-01-24 Rekai Gonzalez-Alb... cpu-o3: O3 LSQ Generalisation
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference.
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtCommitPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtROBPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtIQPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtLSQPolicy a Param.ScopedEnum
2019-01-17 Nikos Nikoleriscpu-o3: Make the smtFetchPolicy a Param.ScopedEnum
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific...
2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
2018-12-22 Gabe Blackcpu: Stop using unions to store FP registers.
2018-12-20 Gabe Blackarch, cpu: Remove float type accessors.
2018-12-11 Pau Cabrecpu: Fixed typos in parameter/stats descriptions
2018-12-11 Pau Cabrecpu: Added parameters to enable/disable features in...
2018-12-11 Tony Gutierrezcpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor
2018-12-04 Nikos Nikolerisbase, sim: Add missing destructors
2018-12-03 Rekai Gonzalez-Alb... cpu: Change raw pointers to STL Containers
2018-11-28 Pau Cabrecpu: Added new stats to TAGE and LTAGE branch predictors
2018-11-28 Pau Cabrecpu: split LTAGE implementation into a base TAGE and...
2018-11-28 Rekai Gonzalez-Alb... cpu,arch-arm: Initialise data members
2018-11-27 Gabe Blackarch, base, cpu, gpu, mem: Replace assert(0 or false...
2018-11-22 Pau Cabrecpu: Made LTAGE parameters configurable
2018-11-22 Pau Cabrecpu: Fixed useful counter handling in LTAGE
2018-11-22 Pau Cabrecpu: Fixes on the loop predictor part of LTAGE
2018-11-17 Pau Cabrecpu: Fix LTAGE max number of allocations on update
2018-11-17 Pau Cabreconfigs: Added an option for choosing branch predictor...
2018-11-16 Rekai Gonzalez-Alb... cpu: Fix the usage of const DynInstPtr
2018-11-14 Pau Cabrecpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
2018-11-13 Pau Cabrecpu: Fixed PC shifting on LTAGE branch predictor
2018-10-09 Giacomo Travaglinicpu: Fix MinorCPU executing Crypto Instructions
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto AES
2018-10-09 Matt Horsnellarch-arm: AArch32 Crypto SHA
2018-10-01 Giacomo Travaglinicpu: Fix typo in header guard for Noncaching cpu
2018-09-13 Earl OuFix SConstruct for asan build
2018-09-12 Andreas Sandbergcpu: Replace the fastmem with a new CPU model
2018-08-24 Giacomo Travaglinicpu: Stream/SubstreamID support in TrafficGen
2018-08-24 Michiel W. van Tolcpu: Turn BaseTrafficGen numSuppressed into a stat
2018-08-21 Jason Lowe-Powermisc: Appease GCC 8
2018-08-17 Brandon Potterscons,ruby: do not generate unnecessary files
2018-08-10 Bradley Wangcpu: Add hash functionality for RegId class
2018-08-10 Bradley Wangcpu: Removed unnecessary file reg_class_impl.hh
2018-07-25 Giacomo Travaglinicpu: Warn when (un)serializing a traffic generator
2018-07-25 Giacomo Travaglinicpu: Allow creation of traffic gen from generic SimObjects
2018-07-24 Hanhwi Jangcpu-o3: Missing freeing the heads of DepGraph in IQ...
2018-07-13 Andreas Sandbergcpu: Add a Python-enabled traffic generator
2018-07-13 Andreas Sandbergcpu: Support trace termination in BaseTrafficGen
2018-07-13 Andreas Sandbergcpu: Unify error handling for address generators
2018-07-13 Andreas Sandbergcpu: Split the traffic generator into two classes
2018-06-28 Andreas Sandbergcpu: Remove reduntant protobuf includes
2018-06-21 Giacomo Travaglinicpu: Fix bug introduced by RequestPtr type change
2018-06-14 Tuan Tacpu: Prevent suspended TimingSimple CPUs from fetching...
2018-06-14 Tuan Tacpu: add a new instruction type 'Atomic'
2018-06-14 Andreas Sandbergcpu-minor: Remove redundant thread startup call
2018-06-11 Giacomo Travaglinimisc: Using smart pointers for memory Requests
2018-06-11 Giacomo Travaglinimisc: Substitute pointer to Request with aliased RequestPtr
2018-05-29 Giacomo Travaglinicpu: Avoid unnecessary dynamic_pointer_cast in atomic...
2018-04-27 Giacomo Travaglinisim,cpu,mem,arch: Introduced MasterInfo data structure
2018-03-27 Gabe Blackcpu: Remove ExtMachInst typedefs from the O3 CPU model.
2018-03-27 Gabe Blackarch: cpu: Make the ExtMachInst type a template argumen...
2018-03-27 Gabe Blackcpu: Stop extracting inst_flags from the machInst.
2018-03-26 Gabe Blackcpu: Use the new asBytes function in the protobuf inst...
2018-03-26 Gabe Blackarch: Add a virtual asBytes function to the StaticInst...
2018-03-23 Jason Lowe-Powerruby: Make sure addresses print in hex
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