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i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions
[mesa.git]
/
src
/
intel
/
compiler
/
brw_vec4_generator.cpp
2017-05-03
Samuel Iglesias...
i965/vec4: don't modify regioning parameters to the...
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2017-04-14
Matt Turner
i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH...
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2017-04-14
Francisco Jerez
i965/vec4: fix assert to detect SIMD lowered DF instruc...
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2017-04-14
Samuel Iglesias...
i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcod...
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2017-04-14
Samuel Iglesias...
i965/vec4: split d2x conversion and data gathering...
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2017-04-14
Juan A. Suarez Romero
i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT
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2017-04-14
Samuel Iglesias...
i965/vec4: split DF instructions and later double its...
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2017-04-14
Matt Turner
i965: Use source region <1,2,0> when converting to DF.
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2017-03-13
Jason Ekstrand
i965: Move the back-end compiler to src/intel/compiler
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