i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions
[mesa.git] / src / intel / compiler / brw_vec4_generator.cpp
2017-05-03 Samuel Iglesias... i965/vec4: don't modify regioning parameters to the...
2017-04-14 Matt Turneri965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH...
2017-04-14 Francisco Jerezi965/vec4: fix assert to detect SIMD lowered DF instruc...
2017-04-14 Samuel Iglesias... i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcod...
2017-04-14 Samuel Iglesias... i965/vec4: split d2x conversion and data gathering...
2017-04-14 Juan A. Suarez Romeroi965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT
2017-04-14 Samuel Iglesias... i965/vec4: split DF instructions and later double its...
2017-04-14 Matt Turneri965: Use source region <1,2,0> when converting to DF.
2017-03-13 Jason Ekstrandi965: Move the back-end compiler to src/intel/compiler