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sim: Make clock private and access using clockPeriod()
[gem5.git]
/
src
/
mem
/
bus.cc
2013-02-19
Andreas Hansson
sim: Make clock private and access using clockPeriod()
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2013-01-07
Andreas Hansson
mem: Tidy up bus addr range debug messages
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2013-01-07
Andreas Hansson
base: Encapsulate the underlying fields in AddrRange
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2012-11-02
Andreas Sandberg
sim: Move the draining interface into a separate base...
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2012-10-15
Andreas Hansson
Mem: Fix incorrect logic in bus blocksize check
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2012-10-15
Andreas Hansson
Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15
Andreas Hansson
Mem: Use range operations in bus in preparation for...
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2012-10-11
Andreas Hansson
Mem: Determine bus block size during initialisation
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2012-09-21
Andreas Hansson
Mem: Tidy up bus member variables types
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2012-09-20
Anthony Gutierrez
bus: removed outdated warn regarding 64 B block sizes
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2012-09-19
Andreas Hansson
AddrRange: Transition from Range<T> to AddrRange
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2012-08-21
Andreas Hansson
Clock: Move the clock and related functions to ClockedO...
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2012-08-15
Anthony Gutierrez
O3,ARM: fix some problems with drain/switchout function...
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2012-07-09
Andreas Hansson
Bus: Split the bus into separate request/response layers
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2012-07-09
Andreas Hansson
Bus: Add a notion of layers to the buses
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2012-07-09
Andreas Hansson
Bus: Replace tickNextIdle and inRetry with a state...
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2012-07-09
Andreas Hansson
Port: Make getAddrRanges const
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2012-07-09
Andreas Hansson
Port: Add getAddrRanges to master port (asking slave...
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2012-07-09
Andreas Hansson
Port: Move retry from port base class to Master/SlavePort
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2012-05-31
Andreas Hansson
Bus: Split the bus into a non-coherent and coherent bus
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2012-05-30
Andreas Hansson
Bus: Remove redundant packet parameter from isOccupied
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2012-05-30
Andreas Hansson
Bus: Turn the PortId into a transport function parameter
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2012-05-30
Andreas Hansson
Packet: Unify the use of PortID in packet and port
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2012-05-08
Andreas Hansson
MEM: Do not forward uncacheable to bus snoopers
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2012-05-01
Andreas Hansson
MEM: Separate requests and responses for timing accesses
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2012-04-25
Andreas Hansson
MEM: Use base class Master/SlavePort pointers in the bus
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2012-04-25
Andreas Hansson
MEM: Add the PortId type and a corresponding id field...
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2012-04-14
Andreas Hansson
MEM: Remove the Broadcast destination from the packet
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2012-04-14
Andreas Hansson
MEM: Separate snoops and normal memory requests/responses
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2012-03-30
William Wang
MEM: Introduce the master/slave port sub-classes in C++
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2012-03-22
Andreas Hansson
MEM: Unify bus access methods and prepare for master...
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2012-02-24
Andreas Hansson
MEM: Move port creation to the memory object(s) constru...
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2012-02-24
Andreas Hansson
MEM: Fatal when no port can be found for an address
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2012-02-09
Andreas Hansson
MEM: Remove onRetryList from BusPort and rely on retryList
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Geoffrey Blake
CheckerCPU: Re-factor CheckerCPU to be compatible with...
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-16
Gabe Black
Merge yet again with the main repository.
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2012-01-17
Andreas Hansson
MEM: Make the bus default port yet another port
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2012-01-17
William Wang
MEM: Remove the functional ports from the memory system
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2012-01-17
Andreas Hansson
MEM: Separate queries for snooping and address ranges
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2012-01-17
Andreas Hansson
MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-10
Min Kyu Jeong
mem: Change DPRINTF prints more useful destination...
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2011-04-15
Nathan Binkert
trace: reimplement the DTRACE function so it doesn...
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2011-01-08
Steve Reinhardt
Replace curTick global variable with accessor functions.
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2010-08-17
Steve Reinhardt
bus: clean up default responder code.
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2010-01-19
Derek Hower
merge
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2009-10-04
Steve Reinhardt
bus: add assertion to catch illegal retry
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2009-06-05
Nathan Binkert
types: clean up types, especially signed vs unsigned
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2008-07-16
Steve Reinhardt
mem: use single BadAddr responder per system.
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2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2008-10-09
Nathan Binkert
eventq: convert all usage of events to use the new...
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2008-07-15
Steve Reinhardt
Add missing newlines to Bus DPRINTFs.
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2008-06-28
Steve Reinhardt
Automated merge after backout.
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2008-06-28
Steve Reinhardt
Backed out changeset 94a7bb476fca: caused memory leak.
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2008-06-24
Ali Saidi
Automated merge with repo.m5sim.org/m5-stable
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2008-06-21
Steve Reinhardt
Make bus address conflict error more informative
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2008-06-21
Steve Reinhardt
Generate more useful error messages for unconnected...
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2008-03-17
Steve Reinhardt
Restructure bus timing calcs to cope with pkt being...
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2008-02-26
Gabe Black
Bus: Fix the bus timing to be more realistic.
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2008-02-11
Steve Reinhardt
Automated merge with file:/home/stever/hg/m5-orig
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2008-02-11
Nicolas Zea
Bus: Only update port cache when there is an item to...
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2008-02-06
Stephen Hines
Make the Event::description() a const function
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2008-01-02
Steve Reinhardt
Bug fix: functional cache port now needs otherPort...
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2007-10-31
Ali Saidi
no manual changes
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2007-10-31
Steve Reinhardt
Merge in bus DPRINTF changes.
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2007-09-16
Steve Reinhardt
mem: clean up bus/cache DPRINTFs a bit
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2007-09-06
Gabe Black
Merge with head.
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2007-09-05
Ali Saidi
Bus: Fix drain code; old method could return 1 in atomi...
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2007-08-30
Miles Kaufmann
params: Deprecate old-style constructors; update most...
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2007-08-27
Gabe Black
Merge with head
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2007-08-24
Ali Saidi
Mem: Make errors in the memory system be responses...
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2007-08-14
Ali Saidi
Merge IGNORE_STYLE change and my change.
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2007-08-12
Ali Saidi
MemorySystem: Fix the use of ?: to produce correct...
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2007-08-12
Nathan Binkert
merge
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2007-08-10
Ali Saidi
DMA: Add IOCache and fix bus bridge to optionally only...
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2007-08-10
Ali Saidi
Bus: Only call end() on an stl object once in a loop
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2007-08-07
Gabe Black
Merge with head.
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2007-08-05
Gabe Black
Merge with head.
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2007-08-04
Vincentius Robby
port: Implement cache for port interfaces and ranges
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2007-08-03
Steve Reinhardt
merge from head
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2007-08-01
Nathan Binkert
merge: mips fix to getArgument
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2007-08-01
Gabe Black
Merge with head.
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2007-08-01
Gabe Black
Merge with head.
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2007-07-31
Steve Reinhardt
Merge from head.
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2007-07-29
Steve Reinhardt
Merge Gabe's changes from head.
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2007-07-29
Steve Reinhardt
bus: take out response prioritization (timing was messe...
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2007-07-29
Nathan Binkert
merge: style.py fix
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2007-07-29
Nathan Binkert
merge whitespace fixes
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diff to current
2007-07-29
Nathan Binkert
merge whitespace changes
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2007-07-27
Nathan Binkert
Merge python and x86 changes with cache branch
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2007-07-27
Steve Reinhardt
bus: Fix default port handling.
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2007-07-25
Steve Reinhardt
Integrate snoop loop functions into their respective...
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2007-07-24
Gabe Black
Merge with head.
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2007-07-24
Nathan Binkert
Major changes to how SimObjects are created and initial...
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2007-07-22
Steve Reinhardt
Merge from head.
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diff to current
2007-07-22
Steve Reinhardt
Merge more changes in from head.
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2007-07-22
Steve Reinhardt
Merge Gabe's changes with mine.
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2007-07-17
Steve Reinhardt
Make sure responses never get blocked.
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2007-07-16
Steve Reinhardt
Merge from head.
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