mem: Adjust cache queue reserve to more conservative values
[gem5.git] / src / mem / cache / base.cc
2016-03-17 Andreas Hanssonmem: Adjust cache queue reserve to more conservative...
2016-03-17 Andreas Hanssonmem: Create a separate class for the cache write buffer
2016-02-10 Andreas Hanssonmem: Deduce if cache should forward snoops
2015-08-21 Andreas Hanssonmem: Add explicit Cache subclass and make BaseCache...
2015-07-07 Andreas Sandbergsim: Decouple draining from the SimObject hierarchy
2015-07-07 Andreas Sandbergsim: Make the drain state a global typed enum
2015-07-03 Andreas Hanssonmem: Remove redundant is_top_level cache parameter
2015-07-03 Andreas Hanssonmem: Add ReadCleanReq and ReadSharedReq packets
2015-07-03 Andreas Hanssonmem: Allow read-only caches and check compliance
2015-05-05 Andreas Hanssonmem: Snoop into caches on uncacheable accesses
2015-05-05 David Guillenmem: Remove templates in cache model
2015-03-02 Andreas Hanssonmem: Tidy up the cache debug messages
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-02-11 Marco Balbonimem: Clarify usage of latency in the cache
2014-12-23 Mitch Hayengamem: Add parameter to reserve MSHR entries for demand...
2014-09-09 Andreas Hanssonmisc: Fix a number of unitialised variables and members
2014-06-27 Curtis Dunhammem: write streaming support via WriteInvalidate promotion
2014-09-03 Andreas Hanssonmem: Fix a bug in the cache port flow control
2014-07-28 Anthony Gutierrezmem: refactor LRU cache tags and add random replacement...
2013-09-04 Andreas Hanssonarch: Resurrect the NOISA build target and rename it...
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-06-27 Prakash Ramrakhyanimem: Reorganize cache tags and make them a SimObject
2013-06-27 Andreas Hanssonmem: Remove the cache builder
2013-03-26 Rene de Jongmem: Cancel cache retry event when blocking port
2013-01-29 Anthony Gutierrezcache: remove drainManager because it's not used
2013-01-07 Andreas Hanssonsim: Fatal if a clocked object is set to have a clock...
2012-11-02 Andreas Sandbergmem: Add support for writing back and flushing caches
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-09-25 Mrinmoy GhoshCache: add a response latency to the caches
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-22 Andreas HanssonMEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-09 Ali Saidicache: Allow main memory to be at disjoint address...
2012-02-24 Andreas HanssonMEM: Simplify cache ports preparing for master/slave...
2012-02-12 Dam Sunwoomem: fix cache stats to use request ids correctly
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Andreas HanssonMEM: Remove the otherPort from the cache ports
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonMEM: Simplify ports by removing EventManager
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-07 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in mem.
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire...
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-02-23 Lisa Hsucache: Make caches sharing aware and add occupancy...
2009-06-05 Nathan Binkerttypes: clean up types, especially signed vs unsigned
2008-07-16 Steve Reinhardtmem: use single BadAddr responder per system.
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2008-10-09 Nathan Binkerteventq: convert all usage of events to use the new...
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-10 Steve ReinhardtFix #include lines for renamed cache files.
2008-02-10 Steve ReinhardtRename cache files for brevity and consistency with...