ruby: slicc: remove nextLineHack from Type.py
[gem5.git] / src / mem / cache /
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths...
2013-10-17 Matt Horsnellcpu: add consistent guarding to *_impl.hh files.
2013-09-04 Andreas Hanssonarch: Resurrect the NOISA build target and rename it...
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-07-18 Xiangyu Dongmem: Add cache class destructor to avoid memory leaks
2013-06-27 Prakash Ramrakhyanimem: Reorganize cache tags and make them a SimObject
2013-06-27 Andreas Hanssonmem: Remove the cache builder
2013-06-27 Andreas Hanssonmem: Align cache timing to clock edges
2013-06-27 Andreas Hanssonmem: Cycles converted to Ticks in atomic cache accesses
2013-06-27 Andreas Hanssonmem: Remove a redundant heap allocation for a snoop...
2013-05-30 Andreas Hanssonmem: Spring cleaning of MSHR and MSHRQueue
2013-05-30 Andreas Hanssonmem: Fix MSHR print format
2013-04-22 Uri Wienermem: Adding verbose debug output in the memory system
2013-03-27 Mitch Hayengamem: Fix cache latency bug
2013-03-26 Rene de Jongmem: Cancel cache retry event when blocking port
2013-02-19 Andreas Hanssonmem: Fix sender state bug and delay popping
2013-02-19 Andreas Hanssonscons: Fix up numerous warnings about name shadowing
2013-02-19 Andreas Hanssonmem: Enforce strict use of busFirst- and busLastWordTime
2013-02-19 Andreas Hanssonmem: Change accessor function names to match the port...
2013-02-19 Andreas Hanssonmem: Make packet bus-related time accounting relative
2013-02-19 Andreas Hanssonmem: Add deferred packet class to prefetcher
2013-02-19 Andreas Hanssonsim: Make clock private and access using clockPeriod()
2013-02-19 Sascha Bischoffmem: Fix SenderState related cache deadlock
2013-02-19 Andreas Hanssonmem: Add predecessor to SenderState base class
2013-02-15 Andreas Hanssonmem: Tighten up cache constness and scoping
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-01-29 Anthony Gutierrezcache: remove drainManager because it's not used
2013-01-08 Mitch Hayengamem: Make LL/SC locks fine grained
2013-01-07 Andreas Sandbergmem: Fix guest corruption when caches handle uncacheabl...
2013-01-07 Andreas Sandbergmem: Remove the IIC replacement policy
2013-01-07 Andreas Hanssonsim: Fatal if a clocked object is set to have a clock...
2013-01-07 Ali Saidicache: add note about where conflicts are handled
2012-11-02 Andreas Sandbergmem: Add support for writing back and flushing caches
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonFix: Address a few minor issues identified by cppcheck
2012-10-15 Andreas HanssonMem: Use cycles to express cache-related latencies
2012-09-25 Djordje KovacevicMEM: Put memory system document into doxygen
2012-09-25 Mrinmoy GhoshCache: add a response latency to the caches
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-09-11 Andreas Hanssonclang: Fix issues identified by the clang static analyzer
2012-09-11 Lena OlsonCache: Split invalidateBlk up to seperate block vs...
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-08-22 Andreas HanssonPort: Extend the QueuedPort interface and use where...
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-07-27 Anthony Gutierrezcache: don't allow dirty data in the i-cache
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python
2012-07-09 Andreas HanssonPort: Make getAddrRanges const
2012-07-09 Andreas HanssonPort: Add isSnooping to slave port (asking master port)
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort
2012-07-09 Andreas HanssonFix: Address a few benign memory leaks
2012-06-29 Lena OlsonCache: Fix the LRU policy for classic memory hierarchy
2012-06-29 Dam SunwooMem: fix master id assertion in cache_impl.hh
2012-06-29 Ali SaidiCache: Only invalidate a line in the cache when an...
2012-06-07 Ali Saidimem: Delay deleting of incoming packets by one call.
2012-06-05 Ali Saidisim: Remove FastAlloc
2012-05-30 Andreas HanssonBus: Turn the PortId into a transport function parameter
2012-05-30 Andreas HanssonPacket: Unify the use of PortID in packet and port
2012-05-24 Andreas HanssonCache: Remove dangling doWriteback declaration
2012-05-10 Ali SaidiCache: restructure code that actually isn't a loop
2012-05-10 Ali Saidigem5: fix some iterator use and erase bugs
2012-05-10 Ali Saidigem5: Fix a number of incorrect case statements
2012-05-10 Ali SaidiCache: Panic if you attempt to create a checkpoint...
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-22 Andreas HanssonMEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-09 Ali Saidicache: Allow main memory to be at disjoint address...
2012-03-01 Ali SaidiCache: Fix an issue with LRU when bonus block is used...
2012-02-24 Andreas HanssonMEM: Simplify cache ports preparing for master/slave...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-12 Dam Sunwoomem: fix cache stats to use request ids correctly
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-12 Mrinmoy Ghoshprefetcher: Make prefetcher a sim object instead of...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Andreas HanssonMEM: Remove the otherPort from the cache ports
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 William WangMEM: Remove the functional ports from the memory system
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonMEM: Remove Port removeConn and MemObject deletePortRefs
2012-01-17 Andreas HanssonMEM: Simplify ports by removing EventManager
2012-01-17 Andreas HanssonMEM: Differentiate functional cache accesses from CPU...
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of includes of config/full_system.hh.
2011-11-07 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in mem.
2011-10-31 Gabe BlackGCC: Get everything working with gcc 4.6.1.
2011-09-13 Ali SaidiPrefetch: Don't prefetch if address is in the write...
2011-09-01 Lisa HsuFix build for gcc-4.2 opt/fast
2011-08-19 Ali SaidiMem: Put prefetcher notify call before packet is deleted.
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