git.libre-soc.org Git - gem5.git/log

arch,sim: Stop decoding the pseudo inst subfunc value.

This isn't used by anything any more. The func field is left in place
to ensure compatability, but there's no reason to decode a value
nobody is going to use.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I85fcd0e4a362551c29af6bff350d99af86050415
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23179
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Use the guest ABI mechanism with pseudo instructions.

Right now, there are only two places which call the pseudoInst function
directly, the ARM KVM CPU and the generic mmapped IPR. These two
callers currently use the generic "PseudoInstABI" which is just a
wrapper around the existing getArgument function.

In the future, this getArgument function will be disolved, and the
PseudoInstABI will be defined for each ABI. Since it currently mimics
the Linux ABI since gem5 can only handle one ABI at a time right now,
this implementation will probably be shared by linux system calls,
except that the pseudo inst implementation will eat return values since
those are returned through other means when the pseudo inst is based on
magic address ranges.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ied97e4a968795158873e492289a1058c8e4e411b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23178
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Semihosting, specify files root dir

This patch adds an option to "ArmSemihosting" which allows for
specifying an optional search path for host files.
Previously, behaviour was fixed to search in the directory from where
the gem5 binary was run from.

Change-Id: I57b932b38d022f132af78857104633d7bfdd1442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23903
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix SMMUv3 walkMasks in page table ops

The masks did not include the high bits above the active addressing
bits.
This could cause overlapping issues when using high addresses.
(Translated with TTBR1)

Change-Id: Ib705558aac456c1b3f069e1bd3ccdd9229a1c1d2
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix SMMUv3 16KB next-level table address masking

The next-level table address for a granule size of 16KB is retrieved
from the 47:14 bits of the current table descriptor (instead of
47:12, which is the valid masking for a 4KB granule)

Change-Id: I570138a34003dc034d8e67dc1209316157d57205
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel van Tol <michiel.vantol@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23763
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour

Architecture states write accesses to GICR_ICFGR0 are WI. This patch
implements handling of this behaviour instead of crashing as an invalid
offset. This is required to support certain software behaviour.

Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Avoid write merging if there are reads in between

This CL reworks the logic in the MSHR to make sure we do not coalesce
requests unless there is a series of write requests for the whole
cache block without any other incompatible requests (e.g., read) in
between.

Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23666
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

configs-arm: enable PMU instantiation in CpuCluster

This patch adds a new method to the CpuCluster object
which allows passing the PMU interrupt numbers and events
to record for each core.
This lets users create CPU clusters with PMUs.

Change-Id: Id49fd0aee50f49e4c6fca95e4ee673da3dca73cd
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22848
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Move destructor of Port to public

To preventing from instantiating an abstract class, hiding its
constructor is enough. Moving destructor to public doesn't break this
intention. This also makes us can use smart pointer to manage derived
Port class.

Change-Id: Ic9cf97e90a6c26108d359eb459df48cd23eaf15c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23925
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix issue with MinorCPU predicated-false mem. accesses

The code block was relying on passed_predicate only (conditional
execution). This was not covering the case where the instruction
gets executed, but the predicate register is false. Using the inLSQ
variable is covering both cases and it makes more sense in terms of
readibility.

Change-Id: Ie1954f37968379a5bda9d0dc9f824a68304cc229
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23280
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Disable MinorCPU value forwarding with write strobes

Change-Id: I7cb50b80b70fcf43ab23eb9e7333d16328993fe1
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19173
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added 'fastmodel' to MAINTAINERS

Gabe Black added as the maintainer.

Change-Id: I69273d090bf17da4e54f50340a33a589fdc63c51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23963
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix compilation errors

This changes fixes two compilation errors when compiling with
FastModels. One is that CurrentMsn should be Iris::CurrentMsn and the
other is that currEL() function needs arch/arm/utility.hh header file.

Test by compiling GEM5 with FastModels:
scons -j64 build/ARM/gem5.opt \
  USE_ARM_FASTMODEL=1     \
  PVLIB_HOME=...          \
  MAXCORE_HOME=...        \
  ARMLMD_LICENSE_FILE=... \

Change-Id: Iabe0a5f25246591f99b57219428b8f87ecd3363c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23924
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC.

Now that the IRIS thread context can be specific to ARM, some things
which had been pushed to a different level of abstraction can be mvoed
back. This will hopefully allow more code sharing in the future when
other types of CPUs are supported.

Change-Id: Ic3a5f0db53ebe93e18f7507ed71812bce27b6d01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23788
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Move the ARM IRIS threadcontext into CortexA76.

This specialization will correspond specifically with the CortexA76,
instead of specializing the ThreadContext for ARM in general. Some
aspects of this class may need to move into the base IRIS thread
context class, but I'll leave that for a later change.

Change-Id: I9cbe527d36e6fda78601dc39c1963370cfa28b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23787
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU.

Fast models are in practice only ARM, so it's not that helpful to have
the ARM-ness factored out. It is, however, helpful to have aspects
which control how gem5 concepts like registers are mapped to fast model
concepts like resources, especially since these mappings may vary from
fast model to fast model.

For instance, it looks like the CortexA76 does not have predicate
vector registers. Rather than make all fast models support or not
support those registers, that can be done on a model by model basis.

Change-Id: I195da4a2f4d2f8593032d0d63e9fd3d20a240d01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23786
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Checkpoint the TCs when checkpointing a fast model CPU.

The generic thread context checkpointing code can be used which calls
into the ThreadContext methods to read the required state.

Change-Id: Ib5c318ff4d2e756274b4c90b56533b2689a837f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23785
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Handle "special" vector regs without calling into IRIS.

These registers don't have an architectural equivalent, but they may
need to be accessed by generic code, for instance the code that
checkpoints a thread context.

Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement readVecRegFlat for ArmThreadContext.

This just calls readVecReg after constructing a RegId.

Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Determine what space to use for breakpoints dynamically.

This was hardcoded as 5, but should be determined based on the memory
space IDs the fast model returns. What we do now is have a specific
override for ARM (perhaps conceptually the A76) which looks for an
address space called "Current" which seems to work well.

It's possible that the appropriate address space for a different model
might have a different number, or even a different name. This may need
to be further specialized/parameterized in those cases.

Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement PC based events.

These use the IRIS breakpoint API to stop the models at the appropriate
points. There seems to be a slightly wonky interaction between
breakpoints and stepping, where if you stop at a breakpoint and then
step, you might end up moving forward more than the number of requested
instructions.

Change-Id: I31f13a120cfc1ad2ec3669ee8befd6d21b328bb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22122
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Always print stderr in gem5 Fixtures

At the moment is impossible when observing an upstream kokoro failure
to understand what went wrong.
This is because the only thing that gets printed is the exception
traceback and the command line generating it.

Most of the time it will be something like

Traceback (most recent call last):
  File
"/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/runner.py", line
195, in setup
    fixture.setup(testitem)
  File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line
115, in setup
    self._setup(testitem)
  File "/tmpfs/src/git/jenkins-gem5-prod/tests/gem5/fixture.py", line
160, in _setup
    log_call(log.test_log, command)
  File
"/tmpfs/src/git/jenkins-gem5-prod/tests/../ext/testlib/helper.py", line
103, in log_call
    raise subprocess.CalledProcessError(retval, cmdstr)

With this patch we dump the stderr so that the fail reason is exposed
to the viewer.

Change-Id: Ic3d0fe75ec4d0543d95e9624dc5287afb4af3b8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23843
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

base: Fix negative op-assign of SatCounter

The value of the add and subtract assignment operations can be negative,
and this was not being handled properly previously. Regarding shift
assignment, the standard says it is undefined behaviour if a negative
number is given, so add assertions for these cases.

Change-Id: I2f1e4143c6385caa80fb25f84ca8edb0ca7e62b7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23664
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: arm realview(64) regressions using VExpress_GEM5_V1

This patch is updating the arm regression configs so that the newer
VExpress_GEM_V1 platform is used instead of the older VExpress_EMM and
VExpress_EMM64.
A new optional kernel_mode argument has been added in order to
distinguish between realview and realview64 platforms. If not provided
the config will assume the machine is running a AArch64 kernel.

Other notable additions:
- DTB autogeneration in regressions
- Using minimal m5exit.squashfs disk image

Change-Id: Ia230565f072fe3eb7756c41876dba4657583f4df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22687
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

systemc: Fix tlm2 socket integration

This change will make the systemc extension in gem5 more compatible to
the reference implementation by Accellera.

* Remove the alias of sc_port's bind in initiator socket.
* Ignore -Woverloaded-virtual in initiator socket.

Change-Id: I229e4d493e01d26174c5662ad71d4859d546d307
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23864
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Fix clang warnings

Fix some warnings reported by clang.

* missing override in {freebsd,linux}/process.hh

Change-Id: I67c36a0785ac90614211d640fd58d3ffe187c17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23863
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix decoding of LDFF1x scalar plus scalar

First-faulting loads do allow Rm == 0x1f.

Change-Id: Ib9bcb55e126653813fdbb7c29970af23a2471ebb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23803
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Semihosting, fix SYS_FLEN

SYS_FLEN was incorrectly handled as SYS_ISTTY. This patch fixes this
behaviour.

Change-Id: I66e0b97d8b44d2cb78e0b1bb940fd6f4b52c658f
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23752
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: kernelExtras optional load addresses

This patch provides a new "System" parameter named "kernel_extras_addrs".
This allows to optionally specify fixed load addresses for the
additional kernel objects. This is useful to load arbitrary blobs into
memory.

Change-Id: I4725763b86c29f72282d1c184d4284d90f9d3016
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23566
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: fix "fatal" usage in fdthelper

"fatal" was not correctly imported in the fdthelper module,
which caused a crash when reporting errors.

Change-Id: I7ee9dcde1f0288e11e56dba67ead4aa2d6d67e02
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23753
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Secure EL2 checking

This patch adds Armv8.4-SecEL2 checking. Helpers implementing
EL2Enabled, IsSecureEL2Enabled and HaveSecureEL2Ext following
the architecture pseudocode are provided. These are intended
to be used for checking register access permissions.

Change-Id: I3d06d0127cf165c1eeaf3302830742d610cef719
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23766
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: AArch64 trap check, arbitrary ECs/Imms

This patch generalises trap checking when accessing system registers
in AArch64. Depending on the accessed register, a different Exception
Class (EC) and immediate value may be set.
Previously this only took SIMD traps into account.

Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Fix some bugs with KVM in SE mode on Intel machines.

The granularity bit should be set since the segment limit should be
interpreted as a number of pages, not bytes.

A comment indicates that NX support is enabled, but the bit wasn't
being set. That's now set to be consistent with FS mode.

The SVME bit is now turned off, since Intel CPUs don't have SVME, and
enabling it apparently makes them upset.

Also disable CR4 bits which enable features neither gem5 nor apparently
my workstation support.

Change-Id: I72d5a07871dede8763b0dd188a52fe5eb6bde6ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23361
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Include some required headers in the syscall debug macros header.

Everything that includes syscall_debug_macros.hh and uses the macro in
it will need these headers, so they should be included through
syscall_debug_macros.hh. The consumer shouldn't have to know what the
macros use internally and to include extra headers to support them.

Change-Id: I9bfa932368daec0772d552357ecad8790b4cfead
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23459
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

fastmodel: Tell fast model not to shutdown when time stops.

Change-Id: I000e7809a2c8850eb31e5615caf1d88b537fea8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22121
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Implement port proxies.

This plumbing is simple and largely copied from other implementations
within gem5. This mechanism should be refactored so that the
duplication is unnecessary.

Change-Id: Ibcdf759b7fba1d574e8e2ba04249afdd92c6560c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22120
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Create a TLB model which uses IRIS to do translations.

Change-Id: I806dc8cdacce57e6ec31d2421b9e6b9733c7da02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22119
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Add an address translation mechanism to the ThreadContext.

This will be used by the TLB to do the actual translation.
Unfortunately there isn't a great way to tell what translation type to
use, so we just go through all of them for now. The ARM subclass might
specialize and figure out which address spaces to use based on control
register state.

Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add Giacomo Travaglini to PMC

Change-Id: I025a4bcde558187d02a7e13c6d644555f7148676
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23723
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix AddrRange::isSubset() check

Making _end non-inclusive, introduced a bug in isSubset() which was
checking if _end is included in the input address range. This CL
changes the behavior and now we test if _end - 1 is in the range.

Change-Id: Ib8822472b7c266e10d55f3d5cf22a46aa45c1fc7
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23663
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Setup Kokoro to run the GTest suite.

Change-Id: If700eed24b2902d04a9b0ee72b72e9e6a3472ef5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23724
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Added channel_addr.cc dependency to channel_addr GTest

In some circumstances not including channel_addr.cc as a dependency for
the channel_addr.test compilation resulted in a build failure (this was
observed in gem5's Kokoro CI system). This commit fixes this problem.

Change-Id: Ic38a104a1e6bf655fc64158b556e6227d5ac3981
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add a header for IRIS MSN constants.

Change-Id: I06a7d7db95ec1ce65945c9e09f812f0b69aaa8e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23643
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

config: Default the indirect branch predictor to "None".

Other scripts (like se.py) blindly try to apply the indirect predictor
if one is set. Because this option defaults to something, there's no
way (as far as I know) to purposefully select nothing, and so the
simulator crashes. Users shouldn't have to proactively prevent gem5
from killing itself regardless, so the default was changed to "None".

Change-Id: Ic3382b8065442d6705b1c6a656646598d9d5c322
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23360
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: kernelExtras if no kernel provided

kernelExtras facilitates a way for users to provide additional
blobs to load into memory. As of now, the creation of the extra
images is done independently of the kernel being provided, but
the loading is only done if the kernel is present.

This patch refactors the loading of extra images to be committed
if no kernel is present.

Change-Id: I900542e1034ade8d757d01823cfd4a30f0b36734
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22850
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-virtio,configs: expose 9p diod virtio on ARM

9p allows the guest Linux kernel to mount a host directory into the guest.

This allows to very easily modify test programs after a run at the end of
boot, without the need to re-insert the changes into a disk image.

It is enabled on both fs.py and fs_bigLITTLE.py with the --vio-9p
option.

Adapted from code originally present on the wiki: http://gem5.org/WA-gem5

As documented in the CLI option help, the current setup requires the guest
to know the full path to the host share, which is annoying, but overcoming
that would require actually parsing a bit of the protocol rather than just
forwarding everything to diod.

Change-Id: Iaeb1ed185dccfa8332fe6657a54e7550f64230eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22831
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-virtio: VIO9P turns on diod verbose output with -d 1

Change-Id: I97e5762f4aca384068b87e22902e071fa3014ceb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22829
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

dev-virtio: don't set the 9p default root

It is better to force users to explicitly set this argument, since
it is unlikely that we will find one safe option for all users.

Change-Id: I612520a44efd205a029a40cd13402584d16e1d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22828
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-virtio: use diod basename as the default 9p path

This allows diod to be present anywhere in the PATH by default,
which works because we are already using execlp.

Change-Id: I9d0b6c9a75f32cf0cb5d8f52bb00c465e4d43e1b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22827
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Encapsulate mapping gem5 to host address space

Create a function to encapsulate mapping an address in gem5's
address space to the host's address space. The returned value can
be used to access the contents of the given address.

As a side effect, make the local variable hostAddr use snake_case
to comply with gem5's coding style.

Change-Id: I2445d3ab4c7ce5746182b307c26cbafc68aa139c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22610
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Move unused prefetches counter update

The number of unused prefetches should be updated every time
a block is invalidated, therefore we move the update to within
the corresponding function.

Change-Id: If3ac2ea43611525bd3c36d628d88382042fcb7dc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18908
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

python: Convert terminal escape sequences to strings.

In python 3, the curses escape sequences are bytes objects and not
strings, making them unsuitable to concatenate to strings which are
being print()-ed. This uses the decode() method to turn them from bytes
objects into string objects, assuming they represent UTF-8. In python
2, bytes objects and strings are treated interchangeably, and so this
isn't necessary.

Change-Id: Ifc5d788e1c62751090a350d3a064e89f434559e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23265
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Always initialize SVE memData

Some compilers will produce a warning when using an uninitialized
memData.

JIRA: https://gem5.atlassian.net/browse/GEM5-196

Change-Id: I19e197b15729a03da546a0188917a9b3e7bf31b7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23525
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Avoid creating an empty byteEnable vector

This behaviour will be forbidden in following patches.
Instead, create an all true vector.

JIRA: https://gem5.atlassian.net/browse/GEM5-196

Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Replace empty byteEnable check with Request::isMasked

This should be the interface to be used to check if the request
has some masked bytes.

JIRA: https://gem5.atlassian.net/browse/GEM5-196

Change-Id: I1ab5fd266c7b63a928aada32ae6d4f7fa915f2b6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23523
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix coding style (byteEnable->byte_enable)

Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

cpu: Add byteEnable assertions to readMem and initateMemRead

Those are already present in writeMem; looking for consistency

Change-Id: Ib85e0db228bc73e3ac64155d1290444cf6864a8c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23281
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

sim,arch: Collapse the ISA specific versions of m5Syscall.

The x86 version doesn't do anything x86 specific, and so can be used
generically in sim/pseudo_inst.(hh|cc)

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu,sim: Push syscall number determination up to processes.

The logic that determines which syscall to call was built into the
implementation of faults/exceptions or even into the instruction
decoder, but that logic can depend on what OS is being used, and
sometimes even what version, for example 32bit vs. 64bit.

This change pushes that logic up into the Process objects since those
already handle a lot of the aspects of emulating the guest OS. Instead,
the ISA or fault implementations just notify the rest of the system
that a nebulous syscall has happened, and that gets propogated upward
until the process does something with it. That's very analogous to how
a system call would work on a real machine.

When a system call happens, the low level component which detects that
should call tc->syscall(&fault), where tc is the relevant thread (or
execution) context, and fault is a Fault which can ultimately be set
by the system call implementation.

The TC implementor (probably a CPU) will then have a chance to do
whatever it needs to to handle a system call. Currently only O3 does
anything special here. That implementor will end up calling the
Process's syscall() method.

Once in Process::syscall, the process object will use it's contextual
knowledge to determine what system call is being requested. It then
calls Process::doSyscall with the right syscall number, where doSyscall
centralizes the common mechanism for actually retrieving and calling
into the system call implementation.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

x86: Stop manually clearing RFLAGS.RF after a system call.

The system call stub KVM uses in SE mode to call the system call
pseudo instruction which ultimately calls m5Syscall already uses
sysret, and the implementation of sysret clears both the RF and VM bits
itself. There's no reason to do that again explicitly here.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Id7b5417564e3f3492ba6efb8ed36fab2f4c38e09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Get rid of the now unused setSyscallArg.

Setting syscall args isn't really something we need to do in gem5,
since that will be taken care of by the code actually calling the
syscall. We just need to be able to retrieve the value it put there.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Stop using setSyscallArg to set argc and argv.

In Alpha and MIPS, the argc and argv values should be in what happens
to be the first and second syscall argument registers, but that's not
by definition. The process objects of both those ISAs know what
registers to use intrinsically, so there's also no reason to call out
to a helper method which acts as a part of the Process's interface to
the rest of gem5.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Id8fa38ab1fc2ac6436e94ad41303439973fded10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23173
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a wrapper/subclass for SyscallDesc which uses GuestABI.

This will let system call implementations take arguments naturally,
and centrally defined, potentially complex, and ISA/context specific
mechanisms will automatically gather the arguments and store any
result.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I68d265e0bab5de372ba975e4c7e9bb2d968c80af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a mechanism to translate ABIs to call host funcs from a TC.

The guest ABI is specified as a template parameter. This makes it
possible for host simcall handlers to be called through different ABIs
which might be from different ISAs, or might be from different contexts
within the same ISA (32 vs 64 bit, syscall vs. function vs.
pseudo instrunction vs. semihosting call).

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I66a0f558e9c1f70a142b69b0dd95bd71e41d898b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23171
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the now unused SyscallDesc flags and methods.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Icee18a4bd77a346d7f82ef4988651b753392d51e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23170
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I9bbffcc74ec4f3df4effa5c50f0a4a688c5b6016
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23169
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Reintroduce the ignoreWarnOnceFunc syscall handler.

Instead of just using warn_once, we'll gate each warning on a bool
which is associated with the syscall desc pointer. To avoid having to
keep warn once bookkeeping in every syscall desc, we put it in a map
which is looked up at runtime.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I1dcce48de91b8a635f9f3df3bfc0ed6ba1291c4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23168
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

sim: Make the syscalls use the SyscallReturn suppression mechanism.

This, among other things, prevents them from needing to toggle global
flags in the syscall desc table to control local behavior.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Idcef23766084f10d5205721b54a6768a850f7eb9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23167
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

dev-arm: GenericTimer, configurable base and low freqs

Architecture states the system counter has a fixed base frequency
provided in the first entry of the frequency modes table. Optionally,
other lower frequencies may be specified in consecutive entries.

This patch adds configurable frequencies to the GenericTimer model.
The default base frequency is kept as the one that was previously
hardcoded for backwards compatibility.

The table is not recommended to be updated once the system is running.

Change-Id: Icba0b340a0eb1cbb47dfe7d7e03b547af4570c60
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22425
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: GenericTimer, freq as 32-bit value

The System Counter frequency is now a 32-bit value. This is consistent
with CNTFRQ and CNTFRQ_EL0 register sizes.

Change-Id: I39886a3767adbe9c58887b8b6d5f30ebc6035bcc
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22424
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Disambuiguate NumFloatV7ArchRegs usage

Sometimes NumFloatV7ArchRegs is used to specify the maximum number of
AArch32 floating point registers. Sometimes it is just used for indexing
a free register storage to be used by microcode. In that scenario,
VecSpecialElem should be used, which is a index to the first available
non architectural register for floating point.

Change-Id: I4e84740701f0e7041cf1acad2afed471361c423a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23107
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Unify VLdmStm behaviour when reg out of index

The generic VLdmStm class (modelling A32 VLDM/VSTM) is handling a wrong
register list in a inconsistent way. Some instructions are opting
for being decoded as Unknown, while others handle it inside the
macro instruction constructor by manually adjusting the reglist.

Those are two valid implementation of the CONSTRAINT UNPREDICTABLE
behaviour (1 and 3):

"If regs > 16 || (d+regs) > 32 , then one of the following behaviors must
occur:
1) The instruction is UNDEFINED .
2) The instruction executes as NOP .
3) One or more of the SIMD and floating-point registers are UNKNOWN . If
the instruction specifies writeback, the base register becomes UNKNOWN .
This behavior does not affect any general-purpose registers."

This patch unfies the behaviour by always opting for option 1) over 3)

Change-Id: I4f98409243d5a2ec64113fe9c87e961a391abe94
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23106
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix NumVecV7ArchRegs value (64->16)

In armv7 there are 16 only quadword (vector) registers which are usable
by SIMD instructions (Q0-Q15). Those completely overlap with the 32
double word registers (D0-D31).

NumVecV7ArchRegs = 16; // Q0-Q15

Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reorder arch/arm/registers.hh constants

This is putting some order in the constants definition, respecting
the description which divides:

* Constants Related to the number of registers
(example: const int NumFloatRegs = 0)

from:

* Semantically meaningful register indices (to indicate special
registers)
(example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs)

Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs

gem5-ARM is not using floatRegs anymore and moved towards the
vecRegs register file (which is used for SIMD&FP + SVE instructions)

Change-Id: I41cfbe10565e4e0db838f98626310a5b14edadb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23103
Tested-by: kokoro <noreply+kokoro@google.com>

tests: AArch64 Linux as quick regressions (instead of AArch32)

NOTE: Following the discussion on the current patch review, some
regressions have been moved to the long list (realview64-simple-atomic
and realview64-simple-timing) in order to reduce computation time. These
should be moved back to the quick list as soon as we get more computing
power.

Change-Id: I07b98c968ad35bf4c7b3646cb72d870e6b07b0d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22686
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

mem: Add Request::isMasked to check for byte strobing

This is trying to overcome the following problem: At the moment a memory
request with a non empty byteEnable mask will be considered masking even
if all elements in the vector are true.

Change-Id: I16ae2c0ea8c3f3370e397bab9d79d6d60c3784bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23284
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add byteEnable copy to Request copy constructor

Change-Id: Ie97543e62524bb244ae65eef096411af4605c175
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23283
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Increase jenkins test timeout to 4 hours.

Change-Id: I11d36a429254df01a46040325baff5b7d18e22b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23463
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: set MaxMiscDestRegs to 2

In an earlier patch, the FCSR was split into its two components, FRM and
FFLAGS, causing explicit writes to FCSR to incur two CSR writes. With
the O3 CPU model, which defers them both to later, this creates a bug
where an assertion that the number of CSR writes must be less than
MaxMiscDestRegs fails because that constant is 1. This patch sets it to
2 so the O3 CPU is compatible with this scheme.

Change-Id: Ic3413738c4eebe9f127980d0d0af5033d18468e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23220
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Set the partial linking group for EXTRAS dirs.

Partial linking heuristically links together files in the same
directory by setting a special automatic tag. That tag needs to also
be maintained when scanning EXTRAS dirs so that they don't all get
lumped in with the last normal directory that was processed.

Change-Id: I2408ea0a1eeffcf6d9994c36415a35760b225b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23300
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Fixes to improve python 3 support.

Some simple fixes to improve python 3 compatability in scons.

Change-Id: I89aba6ed9d73ee733307c57e033c636029d9cb7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23264
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a git commit-msg hook

Add a git commit-msg hook that verifies that commit messages follow
gem5 guidelines.

Commit messages must contain the following components:
    <gem5_tags>: <title>

    <description>
    <patch_tags>

<gem5_tags> are comma separated keywords (found in MAINTAINERS) that
describe which sections of gem5 are being modified by the patch.
Two special keywords can also be used to imply that the author is
looking for feedback on the way their commit was implemented (RFC),
and to inform that the commit is a work in progress (WIP).

<title> A short and concise description of the commit without trailing
whitespaces

<description> is an optional (yet highly recommended) detailed
description of the objective of the commit.

<patch_tags> describe the metadata of the commit, and most of them
are automatically added by Gerrit.

Change-Id: Ib6fb6edf6d1417bfda23729b35c5b8ed44d2cf51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21739
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

kvm,arm: Update the KVM ARM v8 CPU to use vector regs.

The exact mapping of the KVM registers and the gem5 registers is direct and
may not actually be correct.

Change-Id: Idb0981105c002e65755f8dfc315dbb95ea9370df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23402
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: fix asmtest concurrent issues.

riscv asmtest uses multiprocessing.Pool to run multiple gem5
processes concurrently.

By using gem5 default options, processes will fail because:
- accessing to the same m5out directory
- listening too many remote gdb ports at the same time

This will set independent m5out directories and disable remote gdb
ports for asmtest gem5 processes.

Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6
Signed-off-by: Xin Ouyang <xin.ouyang@streamcomputing.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22863
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: missing override specifier

Change-Id: I5a6db4632ec5b670cbfeb7d52190a7545c0b985f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23380
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Adding LDDQU instruction

Tested with simple c binaries.

Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu>
Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a suppression mechanism to the SyscallReturn class.

It makes more sense to specify whether something should be returned
based on the return, not intrinsically on the syscall. This is
especially true in cases like execve where the expected behavior
is not constant.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I95b53b6d69445c7a04c0049fbb0f439238d971e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23166
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Small style fixes in sim/syscall_return.hh.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I485004843393c2e10c1ff4dbd84fc30ca4fd490c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23165
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Change the syscall executor to a std::function.

This will enable using other types of callable like a lambda.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: If9f7176205492830824b5fe3c00f2c7710f57f70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23164
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Fix the getresuidFunc prototype.

When the syscall signature was changed to not take a Process pointer,
the prototype for getresuidFunc was not updated.

Change-Id: I887cc3e3aa8483fc608df9963876a0ac6fa2251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23320
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Fix the predecoder's moreBytes method.

Endianness transformation was moved from the CPU into this method,
making the "inst" parameter guest endian instead of host endian. The
emi member of the decoder was set using the betoh method, ensuring that
it was still stored in host order. Unfortunately, the "inst" parameter
was used in some places when setting up the rest of emi.

This change replaces those uses of inst with emi.

Change-Id: I0c7f9a1833db4b64fc1a5015cf10f6ba3f7c26a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Purposefully *expose* bind in the initiator socket.

Apparently the base version of bind actually *is* supposed to be
accessible, so expose it with using instead of hiding it.

Change-Id: Ie762c35d6322e744696ed597189b7773ea68c3b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23322
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Switch the diagnostic pragmas to GCC from clang.

Clang can handle both, and GCC throws a fit if it sees pragmas for
clang.

Change-Id: Ie9f2789f45706223b11ed5acdf8b371de6e7ee24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23321
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: CONTRIBUTING.md to advise linking Jira Issues in commits

Jira Issue: https://gem5.atlassian.net/browse/GEM5-186

Change-Id: I9fa1471627aed139c0ff207e35a32d9faa82eeb8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23261
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,sim-se: move error checks in syscall methods

There is a check on a global flag denoting that the simulator
has been configured to run in fullsystem mode. The check is
conducted at runtime during calls to syscall methods.

The high-level models are checking the flag when the check
could be conducted further down the call chain (nearer to the
actual Process invocation). Moving the checks should result
in less copy-pasta as new models are developed. It might be
argued that the checks should stay in place since an error
would detected earlier; that may be true, but the error
would be the same and the simulation should fail in either
case. This arrangement requires fewer lines of code.

The changeset also changes the check into a fatal error
instead of a panic since usage (in fs mode) should result
in immediate corruption.

Change-Id: If387e27f166ac1374f3fe8b7befe3546e69adba7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23240
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc,fastmodel: Use the gem5_scons error and warning functions.

Use them in place of messing with termcap directly.

Change-Id: I093efa95e6b6ea7af198dc1395dce05ca6d6575f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23263
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Suppress a spurious clang warning in the systemc headers.

Change-Id: Ife2251d370133383debda9b0439cb84eca80978d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix up some lingering Accellera specific code in TLM v1.

This was missed initially, but clang complained about it.

Change-Id: Ie6d240447a74f96faf9da87bd2f1134c1d82be8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23128
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>