Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 13:54:14 +0000 (13:54 +0000)]
add path argument to pinmuxgen function
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 13:34:35 +0000 (13:34 +0000)]
indent and functionify pinmux generator
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 13:33:54 +0000 (13:33 +0000)]
add path option to parse function
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:57:14 +0000 (05:57 +0000)]
class restructure parsing
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:44:53 +0000 (05:44 +0000)]
remove if brackets
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:44:25 +0000 (05:44 +0000)]
remove if brackets
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:34:10 +0000 (05:34 +0000)]
slight style-alteration on pinmap.txt parsing
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:20:20 +0000 (05:20 +0000)]
slight logic change which seems to work on generating mux selector
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:11:58 +0000 (05:11 +0000)]
use assert not if/print/exit
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:05:56 +0000 (05:05 +0000)]
pycodestyle warned variable name l was ambiguous
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 05:04:59 +0000 (05:04 +0000)]
whitespace cleanup
Luke Kenneth Casson Leighton [Fri, 23 Mar 2018 04:51:49 +0000 (04:51 +0000)]
not a fan of brackets on if statements... :)
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 19:12:04 +0000 (19:12 +0000)]
autopep8, whitespace
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 18:46:44 +0000 (18:46 +0000)]
whitespace, autopep8
Neel [Thu, 22 Mar 2018 16:23:34 +0000 (21:53 +0530)]
signal name for pwm0 is pwm, so variables should change to pwm0_pwm and likewise
Neel [Thu, 22 Mar 2018 16:22:48 +0000 (21:52 +0530)]
signal name for spi is "ss" and not "nss"
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 11:57:25 +0000 (11:57 +0000)]
remove muxwire from generator, call from interface_decl instead
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 11:47:20 +0000 (11:47 +0000)]
remove unneeded generic_io import
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 11:38:15 +0000 (11:38 +0000)]
make interface_decl usage generic
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 11:27:49 +0000 (11:27 +0000)]
attempt to add io_interface to iface automatically
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 11:12:41 +0000 (11:12 +0000)]
convert to classes (or functions)
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:57:22 +0000 (10:57 +0000)]
add gitignore for vi swap and pyc files
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:57:06 +0000 (10:57 +0000)]
add gitignore for vi swap and pyc files
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:55:40 +0000 (10:55 +0000)]
whitespace, autopep8
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:30:21 +0000 (10:30 +0000)]
remove unneeded code
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:26:06 +0000 (10:26 +0000)]
import * baaad!
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:15:47 +0000 (10:15 +0000)]
remove N_UART, N_SPI etc.
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 10:15:11 +0000 (10:15 +0000)]
remove hard-coded additions of interfaces, use Interfaces class
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 09:43:22 +0000 (09:43 +0000)]
corrections to inferface reader, add unit tests
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 09:35:35 +0000 (09:35 +0000)]
add interface reader
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 09:02:20 +0000 (09:02 +0000)]
split interface name out as a prefix
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 07:05:53 +0000 (07:05 +0000)]
use auto-generated wiredefs
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 06:37:07 +0000 (06:37 +0000)]
add wiredef auto-generation
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 06:36:47 +0000 (06:36 +0000)]
more alteration of wire_defs to make auto-generation easier
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:51:23 +0000 (05:51 +0000)]
wire_def whitespace cleanup
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:46:58 +0000 (05:46 +0000)]
Revert "more alteration of wire_defs to make auto-generation easier"
This reverts commit
c5846936454d7d0e45aa39a4f16064797908e348.
(actually not easier)
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:39:09 +0000 (05:39 +0000)]
more alteration of wire_defs to make auto-generation easier
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:17:59 +0000 (05:17 +0000)]
re-format wire_def to make it easier to auto-generate
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:11:25 +0000 (05:11 +0000)]
no longer use *interface_def, spi and jtag remove Bit#(1), is this ok?
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:07:01 +0000 (05:07 +0000)]
use auto-generate on interface definitions
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 05:04:15 +0000 (05:04 +0000)]
consistent naming on io interface
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:51:59 +0000 (04:51 +0000)]
update pwm to consistent naming convention
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:49:52 +0000 (04:49 +0000)]
rename twi to consistent naming convention
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:39:49 +0000 (04:39 +0000)]
cell mux naming convention (forgot to save, whoops)
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:39:23 +0000 (04:39 +0000)]
uart naming convention consistency
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:17:18 +0000 (04:17 +0000)]
no longer need MuxInterface class with consistent naming scheme
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 04:11:59 +0000 (04:11 +0000)]
rename cell mux to consistent naming scheme
Luke Kenneth Casson Leighton [Thu, 22 Mar 2018 03:48:36 +0000 (03:48 +0000)]
rename spi to consistent name format
Luke Kenneth Casson Leighton [Wed, 21 Mar 2018 14:11:33 +0000 (14:11 +0000)]
invert uart rx/tx generation to match wiredefs and interfacedef
Luke Kenneth Casson Leighton [Wed, 21 Mar 2018 13:29:38 +0000 (13:29 +0000)]
partial conversion to use ifacedef
Luke Kenneth Casson Leighton [Wed, 21 Mar 2018 06:29:44 +0000 (06:29 +0000)]
make mux_interface a Pin/Interface... getting complicated
Neel [Wed, 21 Mar 2018 05:11:24 +0000 (10:41 +0530)]
updated yml files for bitbucket bot
Neel [Wed, 21 Mar 2018 05:03:33 +0000 (10:33 +0530)]
fixed indentation issue while generating wire definitions for TWI
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 21:54:28 +0000 (21:54 +0000)]
add first auto-generated interface_def (io_interface_def)
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 21:10:28 +0000 (21:10 +0000)]
use ifacefmt function name consistently
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 21:03:37 +0000 (21:03 +0000)]
rename interface format fn
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:43:17 +0000 (17:43 +0000)]
use with to open file
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:39:44 +0000 (17:39 +0000)]
use with statement on bsv_file
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:38:21 +0000 (17:38 +0000)]
add linebreak on long line
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:35:09 +0000 (17:35 +0000)]
add format function
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:18:12 +0000 (17:18 +0000)]
whitespace cleanup (autopep8)
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:17:53 +0000 (17:17 +0000)]
remove hard-coded interface definitions
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 17:09:01 +0000 (17:09 +0000)]
add io_interface spec, fix bug where \n was in spec
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:58:09 +0000 (16:58 +0000)]
add uart interface
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:57:10 +0000 (16:57 +0000)]
add spi interface
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:55:06 +0000 (16:55 +0000)]
add scl interface spec
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:51:24 +0000 (16:51 +0000)]
whitespace cleanup (autopep8)
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:51:00 +0000 (16:51 +0000)]
whitespace cleanup
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:50:34 +0000 (16:50 +0000)]
document Pin class
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:47:16 +0000 (16:47 +0000)]
add sdcard spec-generator
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:37:36 +0000 (16:37 +0000)]
add jtag interface, remove inout param
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:27:53 +0000 (16:27 +0000)]
add Interface class
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:12:36 +0000 (16:12 +0000)]
add io option to Pin
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 16:08:50 +0000 (16:08 +0000)]
add basic test routine for Pin class
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 15:55:30 +0000 (15:55 +0000)]
add pin class for auto-generating interface lines
Luke Kenneth Casson Leighton [Tue, 20 Mar 2018 11:48:28 +0000 (11:48 +0000)]
whitespace cleanup
Neel [Tue, 20 Mar 2018 09:56:52 +0000 (15:26 +0530)]
adding AXI4Lite transactor for now.
Need to add TileLink support as well later.
Neel [Tue, 20 Mar 2018 07:32:02 +0000 (13:02 +0530)]
switching to python2 and added pep8 auto-sorter to make.
Neel [Mon, 19 Mar 2018 12:01:26 +0000 (17:31 +0530)]
adding support for PWM.
Neel [Mon, 19 Mar 2018 10:36:56 +0000 (16:06 +0530)]
defined the user-interface for the memory mapped registers
Support is provided to address registers using 8-bit, 16-bit, 32-bit or 64-bit addressing scheme.
Need to add support for a compressed scheme as well.
Neel [Mon, 19 Mar 2018 02:52:17 +0000 (08:22 +0530)]
decoupling interfaces for IO and memory mapped registers
Neel [Sat, 17 Mar 2018 09:20:25 +0000 (14:50 +0530)]
adding support for JTAG pins
Neel [Tue, 13 Mar 2018 16:44:45 +0000 (22:14 +0530)]
adding support for interface of SD/MMC.
Neel [Tue, 13 Mar 2018 15:37:58 +0000 (21:07 +0530)]
check for pin number consistency.
see #3.
Added check to see if the user input has screwed up the pin numbering in punmap.txt. This check detects for duplicate assignment to Pins or if some pins are missed out on assignment.
Neel [Tue, 13 Mar 2018 12:43:35 +0000 (18:13 +0530)]
renaming params.py to parse.py. Adding checks on input
See #3.
Added check to see if muxed lists and dedicated lists do not have any duplciates. This can simulated by replacing uart1_tx to uart2_tx in pinmap.txt.
Neel [Tue, 13 Mar 2018 12:07:12 +0000 (17:37 +0530)]
adding a sample test where certain IOs have differing number of muxes
Neel [Tue, 13 Mar 2018 12:06:03 +0000 (17:36 +0530)]
mux selection lines for a IO should be log of the number of muxes.
Neel [Tue, 13 Mar 2018 11:16:37 +0000 (16:46 +0530)]
udpated the .gitignore file.
Neel [Tue, 13 Mar 2018 11:13:11 +0000 (16:43 +0530)]
maintaining distinct arrays for muxed and dedicated cells
This allows better structure of code and also handling muxed logic is decoupled from the dedicated pins. Cell mux methods only for muxed IOs is created.
Parsing of pinmap file now happens in params.py
see #1
Neel [Tue, 13 Mar 2018 06:24:19 +0000 (11:54 +0530)]
full support for dedicated pins.
Neel [Mon, 12 Mar 2018 16:34:31 +0000 (22:04 +0530)]
code clean using pep8 and autopep8.
Neel [Mon, 12 Mar 2018 15:40:39 +0000 (21:10 +0530)]
adding synthesize attribute to the module and a print statement for pinmux generation.
Neel [Mon, 12 Mar 2018 12:32:00 +0000 (18:02 +0530)]
partial support for dedicated pins
removed unwanted print statements from scripts
Neel [Mon, 12 Mar 2018 12:22:19 +0000 (17:52 +0530)]
addeds i2c (twi) interface and also support for inouts
Neel [Mon, 12 Mar 2018 08:08:40 +0000 (13:38 +0530)]
Merge remote-tracking branch 'origin/master'
Neel [Mon, 12 Mar 2018 08:08:28 +0000 (13:38 +0530)]
syntax upgrades for python3 and above
Neel Gala [Mon, 12 Mar 2018 07:55:57 +0000 (07:55 +0000)]
Initial Bitbucket Pipelines configuration
Neel [Sun, 11 Mar 2018 17:07:49 +0000 (22:37 +0530)]
change rule names to allow implicit scheduling
When inputs from multiple IO cells drive the same interface/peripheral there needs to be an implicite priority between the rules updating the same wire (going to the interface). The current pinmap in this commit creates the above scenario.
To enable the implicit scheduling the rules names need to be different. This commit ensures this as well
Also currently the ordering is based on the order in which the user provides the two instances. the first instance os uart_rx is given priority over the later instance in the pinmap.txt file.
Neel [Sun, 11 Mar 2018 16:43:31 +0000 (22:13 +0530)]
automated the pinumxing logic
Currently it only supports muxing between inputs and outputs. Handling of inouts will have to be done soon.
Neel [Sat, 10 Mar 2018 17:17:45 +0000 (22:47 +0530)]
initial commit with minimal templates