mesa, glsl: add support for EXT_shader_image_load_formatted

v3: rebase

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

gallium: add support for formatted image loads

v3: rebase
v3: make use of u_pipe_screen_get_param_defaults

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

radv: set ACCESS_NON_READABLE on stores for copy/fill/clear meta shaders

The compiler will emit GLC=1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: Use local buffers for the global bo list.

Even if we don't use local buffers in general. Turns out that even
though the performance is not the best the kernel still does it
better than our own list.

We still have to keep the radv bo list for buffers that are shared
externally.

This improves Talos on lowest quality setting (so as CPU bound as
possible) by ~10% if the global bo list is enabled.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac: Move has_local_buffers disable to radeonsi.

In radv we had a separate flag to actually use it + an env option
to experimentally use it.

The common code setting has_local_buffers to false of course broke
that experimental option.

Also the "enable on APU" did not make sense for RADV as it is still
disabled by default.

Fixes: b21a4efb553 "radv/winsys: allow local BOs on APUs"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Add bolist RADV_PERFTEST flag.

To test global_bo_list performance.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac: fix incorrect bindless atomic code in visit_image_atomic

Coverity: CID 1444664

Fixes: d62d434fe920 ("ac/nir_to_llvm: add image bindless support")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nir,ac/nir: fix cube_face_coord

Seems it was missing the "/ ma + 0.5" and the order was swapped.

Fixes: a1a2a8dfda7b9cac7e ('nir: add AMD_gcn_shader extended instructions')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

anv: Update to use the new features struct names

These were updated in version 1.1.106 of vulkan.h to make more sense
with the extension names.  We may as well keep with the times.

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

vulkan: Update the XML and headers to 1.1.106

Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

nir: fix packing components with arrays

When gathering info for unmovable types we need to handle arrays.
While we dont support packing/moving arrays we do support packing
scalar components with these arrays.

Fixes piglit:
tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test

Fixes: 5eb17506e159 ("nir: do not pack varying with different types")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: enable VK_KHR_shader_float16_int8

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

spirv: add SpvCapabilityFloat16 support

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

intel: Emit 3DSTATE_VF_STATISTICS dynamically

Pipeline statistics queries should not count BLORP's rectangles.

    (23) How do operations like Clear, TexSubImage, etc. affect the
         results of the newly introduced queries?

      DISCUSSION: Implementations might require "helper" rendering
      commands be issued to implement certain operations like Clear,
      TexSubImage, etc.

      RESOLVED: They don't. Only application submitted rendering
      commands should have an effect on the results of the queries.

Piglit's arb_pipeline_statistics_query-vert_adj exposes this bug when
the driver is hacked to always perform glBufferData via a GPU staging
copy (for debugging purposes).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

nir/validate: Require unused bits of nir_const_value to be zero

Reviewed-by: Karol Herbst <kherbst@redhat.com>

nir/load_const_to_scalar: Get rid of a bit size switch statement

Now that nir_const_value is a scalar, we don't need the switch on bit
size in order to pluck off components properly.

Reviewed-by: Karol Herbst <kherbst@redhat.com>

spirv: Drop some unneeded bit size switch statements

Now that nir_const_value is a scalar, we don't need the switch on bit
size in order copy components around properly.

Reviewed-by: Karol Herbst <kherbst@redhat.com>

nir/constant_folding: Get rid of a bit size switch statement

Now that nir_const_value is a scalar, we don't need the switch on bit
size in order to swizzle them properly.

Reviewed-by: Karol Herbst <kherbst@redhat.com>

nir: make nir_const_value scalar

v2: remove & operator in a couple of memsets
    add some memsets
v3: fixup lima

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)

spirv: reduce array size in vtn_handle_constant

we already assert above that there are no more than 3 sources, so it
doesn't make sense to use an array of 4 sources

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/loop_analyze: use nir_const_value.b for boolean results, not u32

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/print: Use nir_src_as_int for array indices

Reviewed-by: Karol Herbst <kherbst@redhat.com>

nir/builder: Add a nir_imm_zero helper

v2: replace nir_zero_vec with nir_imm_zero (Karol Herbst)

Reviewed-by: Karol Herbst <kherbst@redhat.com>

nir/builder: Move nir_imm_vec2 from blorp into the builder

While we're here, fix a typo which caused it to actually return a vec4
with the third and fourth components zero.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

lima: use nir_src_as_float

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

freedreno/ir3: use nir_src_as_uint in a few places

v2 (Jason Ekstrand):
 - Add even more places

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/nir: use nir_src_is_const and nir_src_as_uint

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/nir: Take a nir_tex_instr and src index in brw_texture_offset

This makes things a bit simpler and it's also more robust because it no
longer has a hard dependency on the offset being a 32-bit value.

radv: use nir constant helpers

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

amd/nir: some cleanups

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

panfrost/midgard: Use shared nir_lower_viewport_transform

v2: Run before lowering I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

nir: Add nir_lower_viewport_transform

On Mali hardware (supported by Panfrost and Lima), the fixed-function
transformation from world-space to screen-space coordinates is done in
the vertex shader prior to writing out the gl_Position varying, rather
than in dedicated hardware. This commit adds a shared NIR pass for
implementing coordinate transformation and lowering gl_Position writes
into screen-space gl_Position writes.

v2: Run directly on derefs before io/vars are lowered to cleanup the
code substantially. Thank you to Qiang for this suggestion!

v3: Bikeshed continues.

v4: Add to Makefile.sources (per Jason's comment). Bikeshed comment.

Ian and Qiang's reviews are from v3, but no real functional changes from
v4. Rob's review is from v4.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

panfrost: Cleanup indexed draw handling

As part of this cleanup, we use the newly-exposed
u_vbuf_get_minmax_index, deduplicating quite a bit of bookkeeping. We
also centralize the draw_flags tracking to make this code cleaner /
futureproofed; we have already had bugs regarding this field so we might
as well get it right now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Drop dependence on mesa/st

This was used as a workaround for uniform sizing which was fixed in
771adffe ("st: Lower uniforms in st in the...")

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

draw: fix building error in draw_gs_init()

Fixes the following building error happening with Android build system:

external/mesa/src/gallium/auxiliary/draw/draw_gs.c:740:79:
error: address of array 'draw->gs.tgsi.machine->PrimitiveOffsets' will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion]
         if (!draw->gs.tgsi.machine->Primitives[i] || !draw->gs.tgsi.machine->PrimitiveOffsets)
                                                      ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~
1 error generated.

Fixes: 7720ce3 ("draw: add support to tgsi paths for geometry streams. (v2)")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

lima/gpir: fix alu check miss last store slot

Fixes: 92d7ca4b1cd "gallium: add lima driver"
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima/gpir: fix compile fail when two slot node

Come from glmark2-es2 jellyfish test.

Fixes: 92d7ca4b1cd "gallium: add lima driver"
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>

lima: add support for depth/stencil fbo attachments and textures

Hardware supports writing back Z/S buffers and sampling from them,
so add support for that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>

lima: use individual tile heap for each GP job.

Looks like it's somehow used by subsequent PP job, so we have to
preserve its contents until PP job is done.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>

nir: add lower_ftrunc

Port TGSI TRUNC lowering to nir

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

android: fix LLVM version string related building errors

Adding \ prior to " in llvm version string fixes the following building errors:

external/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1290:14:
error: expected ')'
                 ", LLVM " MESA_LLVM_VERSION_STRING
                           ^
<command line>:8:34: note: expanded from here
                                 ^
external/mesa/src/gallium/drivers/r600/r600_pipe_common.c:1287:10:
note: to match this '('
        snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
                ^
1 error generated.

Fixes: 05b114e ("simplify LLVM version string printing")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>

anv: leave the top 4Gb of the high heap VMA unused

In 628c9ca9089789 I forgot to apply the same -4Gb of the high address
of the high heap VMA. This was previously computed in the
HIGH_HEAP_MAX_ADDRESS.

Many thanks to James for pointing this out.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Xiong, James <james.xiong@intel.com>
Fixes: 628c9ca9089789 ("anv: store heap address bounds when initializing physical device")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

v3d: Use the new lower_to_scratch implementation for indirects on temps.

We can use the same register spilling infrastructure for our loads/stores
of indirect access of temp variables, instead of doing an if ladder.

Cuts 50% of instructions and max-temps from 2 KSP shaders in shader-db.
Also causes several other KSP shaders with large bodies and large loop
counts to not be force-unrolled.

The change was originally motivated by NOLTIS slightly modifying register
pressure in piglit temp mat4 array read/write tests, triggering register
allocation failures.

nir: Add a pass for selectively lowering variables to scratch space

This commit adds new nir_load/store_scratch opcodes which read and write
a virtual scratch space.  It's up to the back-end to figure out what to
do with it and where to put the actual scratch data.

v2: Drop const_index comments (by anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>

v3d: Detect the correct number of QPUs and use it to fix the spill size.

We were missing a * 4 even if the particular hardware matched our
assumption.

v3d: Add missing dumping for the spill offset/size uniforms.

v3d: Add missing base offset to CS shared memory accesses.

This code is so touchy, trying to emit the minimum amount of address math.
Some day we'll move it all to NIR, I hope.

v3d: Add Compute Shader compilation support.

While waiting for the CSD UABI to get reviewed, I keep having to rebase
the CS patch.  Just land the compiler side for now to keep it from
diverging.

For now this covers just GLES 3.1 compute shaders, not CL kernels.

v3d: Replace the old shader-db env var output with the ARB_debug_output.

We're using ARB_debug_output for the main shader-db, but I had this env
var left around from the shader-db-2 support (vc4 apitrace-based).  Keep
the env var around since it's nice sometimes to get the stats on a shader
you're optimizing without having to do a shader-db run, but drop the old
formatting that's not useful and keeps tricking me when I go to add
another measurement to the shader-db output.

v3d: Include the number of max temps used in the shader-db output.

This gives us finer-grained feedback on how we're doing on register
pressure than "did we trigger a new shader to spill or drop thread count?"

v3d: Drop a note for the future about PIPE_CAP_PACKED_UNIFORMS.

v3d: Add and use a define for the number of channels in a QPU invocation.

A shader invocation always executes 16 channels together, so we often end
up multiplying things by this magic 16 number.  Give it a name.

nir: Add a comment about how intrinsic definitions work.

I was thinking about a refactor, and needed to read this first.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Drop remaining references to const_index in favor of the call to use.

Please don't make me read a const_index[] expression ever again.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: Drop comments about the constant_index slots for load/stores.

The constant_index slots are named right there in the intrinsic
definition, and the comment is just a chance to get out of sync.  Noticed
while reviewing the lower_to_scratch changes that copy-and-pasted wrong
comments, and load_ubo and load_per_vertex_output had incorrect comments
currently.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Remove unused condition from opt_algebraic case

We will never hit a condition where we have src1 and src2 as immediate
operands.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: Set location on structure-split sampler uniform variables

gl_nir_lower_samplers_as_deref splits structure uniform variables,
creating new variables for individual fields.  As part of that, it
calculates a new location.  It then never set this on the new variables.

Thanks to Michael Fiano for finding this bug.  Fixes crashes on i965
with Piglit's new tests/spec/glsl-1.10/execution/samplers/uniform-struct
test, which was reduced from the failing case in Michael's app.

Fixes: f003859f97c nir: Make gl_nir_lower_samplers use gl_nir_lower_samplers_as_deref
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

panfrost: use os_mmap and os_munmap

32-bit needs mmap64 for 64-bit offsets. We get 64-bit offsets from kernel.

Signed-off-by: Mateusz Krzak <kszaquitto@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: cast bo_handles pointer to uintptr_t first

Required for 64-bit kernel to interpret the pointer from 32-bit userspace.

Signed-off-by: Mateusz Krzak <kszaquitto@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

anv/pipeline: Fix MEDIA_VFE_STATE::PerThreadScratchSpace on gen7

We were always programming it with the Broadwell convention which is too
large by a factor of two on Haswell and just plain wrong on IVB and BYT.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org

gitlab-ci: add lima to the build

Suggested-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

ac: use the common helper ac_apply_fmask_to_sample

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: set AC_FUNC_ATTR_READNONE for image opcodes where it was missing

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: don't overwrite existing shader files with MESA_SHADER_CAPTURE_PATH

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

glsl: allow the #extension directive within code blocks for the dri option

for Viewperf 13

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

ac/nir: remove some useless integer casts for ALU operations

Sources are always casted to integers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: remove useless integer cast in visit_image_load()

ac_build_image_opcode() casts if necessary and buffer images
are casted too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: remove useless integer cast in adjust_sample_index_using_fmask()

It's already casted if necessary in ac_build_image_opcode().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: remove useles LLVMGetUndef for nir_op_pack_64_2x32_split

Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add ac_build_load_helper_invocation() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add ac_build_ddxy_interp() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac: add ac_build_umax() and use it where possible

This changes the predicate from LessThan to Equal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: make use of ac_build_umin() where possible

This changes the predicate from LessThan to Equal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: make use of ac_build_imin() where possible

This changes the predicate from LessThan to Equal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: make use of ac_build_imax() where possible

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

lima: add bool parameter to type_size function

Fixes: 035759b61ba1778d5143cdf3a8795a62dd5d8a60
       ("nir/i965/freedreno/vc4: add a bindless bool to type size functions")

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

nvc0/nir: enable bindless texture

Signed-off-by: Karol Herbst <kherbst@redhat.com>

nv50/ir/nir: add support for bindless images

Signed-off-by: Karol Herbst <kherbst@redhat.com>

nv50/ir/nir: handle bindless texture

Signed-off-by: Karol Herbst <kherbst@redhat.com>

ac/nir_to_llvm: add image bindless support

With this all piglit bindless image tests pass on radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir_to_llvm: make get_sampler_desc() more generic and pass it the image intrinsic

This will be required by the bindless support in the following patches.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl/nir: add support for lowering bindless images_derefs

v2: handle atomics as well
    make use of nir_rewrite_image_intrinsic
v3: remove call to nir_remove_dead_derefs
v4: (Timothy Arceri) dont actually call lowering yet

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v3)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl/nir: fetch the type for images from the deref instruction

fixes retrieving the sampler type for bindless images stored inside structs.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl_to_nir: handle bindless textures

v2: add support for AMD

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir/i965/freedreno/vc4: add a bindless bool to type size functions

This required to calculate sizes correctly when we have bindless
samplers/images.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: move brw_nir_rewrite_image_intrinsic into common code

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

lima: lower bool to float when building shaders

Both processors of Mali Utgard are float-only, so bool are not
acceptable data type of them. Fortunately the NIR compiler
infrastructure has a lower pass to lower bool to float.

Call this lower pass to lower bool to float for both GP and PP. This
makes Glamor on Xorg server 1.20.3 at least doesn't hang when starting
gtk3-demo.

The old map of nir op bcsel is changed to fcsel, and the map of b2f32 in
PP is dropped because it's not needed now (it's originally only mapped
to ppir_op_mov).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

panfrost: Guard against reading past end of buffer

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: split asserts in pandecode

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

llvmpipe: fix undefined shift 1 << 31.

Pointed out by coverity.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

swrast: fix undefined shift of 1 << 31

Pointed out by coverity

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

draw: fix undefined shift of (1 << 31)

Pointed out by a coverity scan.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

iris: Actually pin the scratch BO.

We were pinning it for compute shaders, and pinning it when restoring
saved buffers, but we never actually pinned it in the original batch
for VS/TCS/TES/GS/FS.

Fixes rendering in GFXBench5's Tessellation demo and a bunch of Piglit
geometry shader tests.

anv: store heap address bounds when initializing physical device

We can then reuse those bounds to initialize the VMA heaps at logical
device creation.

This fixes an issue on EHL which has only 36bits of VMA. We were
incorrectly using the fixed 48bits upper bound to initialize the
logical device heap, resulting in addresses beyong the device's
limits.

v2: Don't confuse heap size (limited by system memory) and VMA size
   (limited by number of addressing bits the platform has)

v3: Fix low heap vma_size :( (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)

intel/common: Support bigger right-shifts with mi_builder

Because why not?

anv/cmd_buffer: Use gen_mi_sub instead of gen_mi_add with a negative

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Move mi_memcpy and mi_memset to gen_mi_builder

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for queries

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for conditional rendering

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: Use gen_mi_builder for indirect dispatch

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>