mesa.git
5 years agointel/fs: Do not lower large local arrays to scratch on gen7
Danylo Piliaiev [Tue, 12 Nov 2019 16:32:25 +0000 (18:32 +0200)]
intel/fs: Do not lower large local arrays to scratch on gen7

On gen7 and earlier the scratch space size is limited to 12kB.
By enabling this optimization we may easily exceed this limit
without having any fallback.

arb_compute_shader/linker/bug-93840.shader_test crashes with
this lowering on IVB due to exceeding scratch size limit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2092
Fixes: 69244fc7
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoutil: Move gallium's PIPE_FORMAT utils to /util/format/
Eric Anholt [Thu, 27 Jun 2019 22:05:31 +0000 (15:05 -0700)]
util: Move gallium's PIPE_FORMAT utils to /util/format/

To make PIPE_FORMATs usable from non-gallium parts of Mesa, I want to
move their helpers out of gallium.  Since u_format used
util_copy_rect(), I moved that in there, too.

I've put it in a separate directory in util/ because it's a big chunk
of related code, and it's not clear to me whether we might want it as
a separate library from libmesa_util at some point.

Closes: #1905
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agogitlab-ci: auto-cancel CI runs when a newer commit is pushed to the same branch
Eric Engestrom [Tue, 12 Nov 2019 23:42:21 +0000 (23:42 +0000)]
gitlab-ci: auto-cancel CI runs when a newer commit is pushed to the same branch

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
5 years agoaco: Optimize out trivial code from uniform bools.
Timur Kristóf [Tue, 5 Nov 2019 10:41:00 +0000 (11:41 +0100)]
aco: Optimize out trivial code from uniform bools.

This should remove most of the excess code size that was
introduced by making all booleans per-lane.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: Treat all booleans as per-lane.
Timur Kristóf [Mon, 4 Nov 2019 18:28:08 +0000 (19:28 +0100)]
aco: Treat all booleans as per-lane.

Previously, instruction selection had two kinds of booleans:
1. divergent which was per-lane and stored in s2 (VCC size)
2. uniform which was stored in s1
Additionally, uniform booleans were made per-lane when they resulted
from operations which were supported only by the VALU.

To decide which type was used, we relied on the destination size,
which was not reliable due to the per-lane uniform bools, but it
mostly works on wave64.
However, in wave32 mode (where VCC is also s1) this approach
makes it impossible keep track of which boolean is uniform and
which is divergent.

This commit makes all booleans per-lane.
The resulting excess code size will be taken care of by the optimizer.

v2 (by Daniel Schürmann):
- Better names for some functions
- Use s_andn2_b64 with exec for nir_op_inot
- Simplify code due to using s_and_b64 in bool_to_scalar_condition

v3 (by Timur Kristóf):
- Fix several subgroups regressions

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: use s_and_b64 exec to reduce uniform booleans to one bit
Daniel Schürmann [Tue, 12 Nov 2019 10:40:28 +0000 (11:40 +0100)]
aco: use s_and_b64 exec to reduce uniform booleans to one bit

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agoaco: Make sure not to mistakenly propagate 64-bit constants.
Timur Kristóf [Wed, 6 Nov 2019 16:42:32 +0000 (17:42 +0100)]
aco: Make sure not to mistakenly propagate 64-bit constants.

ACO's optimizer would try to propagate 64-bit constants, but
does so in such a way that wouldn't work due to how the 64-bit
constants are handled in the IR.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: value number instructions using the execution mask
Daniel Schürmann [Mon, 11 Nov 2019 10:41:31 +0000 (11:41 +0100)]
aco: value number instructions using the execution mask

This patch tries to give instructions with the same execution
mask also the same pass_flags and enables VN for SALU instructions
using exec as Operand.
This patch also adds back VN for VOPC instructions and removes VN for phis.

v2 (by Timur Kristóf):
- Fix some regressions.
v3 (by Daniel Schürmann):
- Fix additional issues

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agoaco: check if SALU instructions are predeceeded by exec when calculating WQM needs
Daniel Schürmann [Mon, 11 Nov 2019 15:21:51 +0000 (16:21 +0100)]
aco: check if SALU instructions are predeceeded by exec when calculating WQM needs

Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agoac: fix build with recent LLVM
Samuel Pitoiset [Thu, 14 Nov 2019 09:04:29 +0000 (10:04 +0100)]
ac: fix build with recent LLVM

Build is broken since "Move CodeGenFileType enum to Support/CodeGen.h".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoRevert "mesa: allow bit queries for EXT_disjoint_timer_query"
Tapani Pälli [Thu, 14 Nov 2019 12:50:30 +0000 (14:50 +0200)]
Revert "mesa: allow bit queries for EXT_disjoint_timer_query"

This reverts commit 66d24a9ef705b8f9f15dab8059b63781f9fb28ca.

This commit made Mesa CI red because commit depends on a Piglit test
change.

5 years agonir: Fix non-determinism in lower_global_vars_to_local
Connor Abbott [Tue, 22 Oct 2019 15:50:07 +0000 (17:50 +0200)]
nir: Fix non-determinism in lower_global_vars_to_local

Using a hash-table walk means that variables will get inserted in
different orders on different runs. Just walk the list of globals
instead, even if some of them can't be turned into locals.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agomesa/st: make sure we remove dead IO variables before handing NIR to backends
Iago Toral Quiroga [Wed, 13 Nov 2019 08:19:22 +0000 (09:19 +0100)]
mesa/st: make sure we remove dead IO variables before handing NIR to backends

Commit "1c2bf82d24a glsl: disable lower_fragdata_array() for NIR drivers"
disabled the GLSL IR lowering that turned gl_FragData from an array into a
collection of scalar outputs under the assumption that this was already being
handled properly elsewhere, however there are some corner cases where NIR
would fail to do this, leaving gl_FragData[] as an array variable. This can
break backends that assume that all their outputs will be scalar and use the
variable definitions from the shader to do their output setup, such as the
case of V3D.

At least one corner case was found in some Portal shaders from shader-db, where
NIR would optimize out the full body of a fragment shader. In this scenario,
the empty shader would keep the original array definition of gl_FragData[],
causing the backend to assert.

We need to do this late enough for it to be effective, since doing it in
st_nir_preprocess does not fix the original problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2091
Fixes: 1c2bf82d ("glsl: disable lower_fragdata_array() for NIR drivers")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agomesa: allow bit queries for EXT_disjoint_timer_query
Tapani Pälli [Tue, 12 Nov 2019 11:43:21 +0000 (13:43 +0200)]
mesa: allow bit queries for EXT_disjoint_timer_query

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2090
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoRevert "dri_interface: add interface for EGL_EXT_image_flush_external"
Tapani Pälli [Tue, 12 Nov 2019 15:33:08 +0000 (17:33 +0200)]
Revert "dri_interface: add interface for EGL_EXT_image_flush_external"

This reverts commit 7520478461d8ab1cda415ff689d6b9058213ff43.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoRevert "st/dri: assume external consumers of back buffers can write to the buffers"
Tapani Pälli [Tue, 12 Nov 2019 15:32:56 +0000 (17:32 +0200)]
Revert "st/dri: assume external consumers of back buffers can write to the buffers"

This reverts commit 1d1b4578211dcc69cfab8879d0cdafaba1eec948.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoRevert "st/dri: add support for EGL_EXT_image_flush_external"
Tapani Pälli [Tue, 12 Nov 2019 15:32:49 +0000 (17:32 +0200)]
Revert "st/dri: add support for EGL_EXT_image_flush_external"

This reverts commit 1d122c104a7a3d9348ab347e1e843b7e2bf3b498.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoRevert "egl: handle EGL_IMAGE_EXTERNAL_FLUSH_EXT"
Tapani Pälli [Tue, 12 Nov 2019 15:32:41 +0000 (17:32 +0200)]
Revert "egl: handle EGL_IMAGE_EXTERNAL_FLUSH_EXT"

This reverts commit 34b1aa957a3f44ea9587ec43311e8434d3782cc1.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoRevert "egl: implement new functions from EGL_EXT_image_flush_external"
Tapani Pälli [Tue, 12 Nov 2019 15:32:33 +0000 (17:32 +0200)]
Revert "egl: implement new functions from EGL_EXT_image_flush_external"

This reverts commit c1c574fdf18f2aeb1c03f9670bf00e1dcd22d99d.

This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agopan/midgard: Fix copypropagation for textures
Alyssa Rosenzweig [Fri, 8 Nov 2019 18:11:25 +0000 (13:11 -0500)]
pan/midgard: Fix copypropagation for textures

total instructions in shared programs: 3562 -> 3457 (-2.95%)
instructions in affected programs: 575 -> 470 (-18.26%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 14 x̄: 6.56 x̃: 10
helped stats (rel) min: 5.71% max: 24.56% x̄: 16.83% x̃: 18.87%
95% mean confidence interval for instructions value: -9.07 -4.06
95% mean confidence interval for instructions %-change: -19.00% -14.66%
Instructions are helped.

total bundles in shared programs: 1846 -> 1830 (-0.87%)
bundles in affected programs: 338 -> 322 (-4.73%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 2.50% max: 20.00% x̄: 8.85% x̃: 3.33%
95% mean confidence interval for bundles value: -1.00 -1.00
95% mean confidence interval for bundles %-change: -13.02% -4.67%
Bundles are helped.

total quadwords in shared programs: 3191 -> 3144 (-1.47%)
quadwords in affected programs: 606 -> 559 (-7.76%)
helped: 16
HURT: 0
helped stats (abs) min: 1 max: 14 x̄: 2.94 x̃: 3
helped stats (rel) min: 5.17% max: 22.22% x̄: 11.20% x̃: 5.62%
95% mean confidence interval for quadwords value: -4.58 -1.29
95% mean confidence interval for quadwords %-change: -15.16% -7.24%
Quadwords are helped.

total registers in shared programs: 312 -> 303 (-2.88%)
registers in affected programs: 27 -> 18 (-33.33%)
helped: 9
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
95% mean confidence interval for registers value: -1.00 -1.00
95% mean confidence interval for registers %-change: -33.33% -33.33%
Registers are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Copypropagate vector creation
Alyssa Rosenzweig [Fri, 8 Nov 2019 18:27:39 +0000 (13:27 -0500)]
pan/midgard: Copypropagate vector creation

total instructions in shared programs: 3457 -> 3431 (-0.75%)
instructions in affected programs: 787 -> 761 (-3.30%)
helped: 14
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 1.86 x̃: 1
helped stats (rel) min: 1.01% max: 11.11% x̄: 9.22% x̃: 11.11%
95% mean confidence interval for instructions value: -3.55 -0.16
95% mean confidence interval for instructions %-change: -11.41% -7.03%
Instructions are helped.

total bundles in shared programs: 1830 -> 1826 (-0.22%)
bundles in affected programs: 279 -> 275 (-1.43%)
helped: 2
HURT: 0

total quadwords in shared programs: 3144 -> 3121 (-0.73%)
quadwords in affected programs: 645 -> 622 (-3.57%)
helped: 13
HURT: 0
helped stats (abs) min: 1 max: 11 x̄: 1.77 x̃: 1
helped stats (rel) min: 2.09% max: 16.67% x̄: 12.61% x̃: 14.29%
95% mean confidence interval for quadwords value: -3.45 -0.09
95% mean confidence interval for quadwords %-change: -15.43% -9.79%
Quadwords are helped.

total registers in shared programs: 303 -> 301 (-0.66%)
registers in affected programs: 14 -> 12 (-14.29%)
helped: 2
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/lcra: Use Chaitin's spilling heuristic
Alyssa Rosenzweig [Wed, 13 Nov 2019 20:57:18 +0000 (15:57 -0500)]
pan/lcra: Use Chaitin's spilling heuristic

Not much of a difference but slightly better and slightly less
arbitrary.

total instructions in shared programs: 3560 -> 3559 (-0.03%)
instructions in affected programs: 44 -> 43 (-2.27%)
helped: 1
HURT: 0

total bundles in shared programs: 1844 -> 1843 (-0.05%)
bundles in affected programs: 23 -> 22 (-4.35%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Compute spill costs
Alyssa Rosenzweig [Sat, 26 Oct 2019 14:08:18 +0000 (10:08 -0400)]
pan/midgard: Compute spill costs

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agointel/compiler: fix nir_op_{i,u}*32 on ICL
Paulo Zanoni [Tue, 12 Nov 2019 00:49:15 +0000 (16:49 -0800)]
intel/compiler: fix nir_op_{i,u}*32 on ICL

On ICL we have the src1 restriction which is applied through
fix_byte_src() and potentially changes the type of the operands from 8
to 32 bits. When this change happens, we fall into the "else if
(bit_size < 32)" case and miscompute src_type because it takes into
consideration bit_size (8) instead of the adjusted size of temp_op
(32). This results in the shader reading unused memory, giving us
mostly failures, but occasional passes due to whatever was already in
the registers we were reading.

This commit fixes a lot of dEQP subgroup i8vec2 tests on ICL, such as:
    dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2

This can also be verified by simply changing fix_byte_src() to apply
on all platforms.

Fixes: 5847de6e9afe ("intel/compiler: don't use byte operands for src1 on ICL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
5 years agospirv: Consider the sampled_image case in wa_glslang_179 workaround
Caio Marcelo de Oliveira Filho [Wed, 13 Nov 2019 19:04:39 +0000 (11:04 -0800)]
spirv: Consider the sampled_image case in wa_glslang_179 workaround

Fixes: 9e440b8d0b9 ("spirv: Sort out the mess that is sampled image")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agodocs: update calendar, add news item and link release notes for 19.2.4
Dylan Baker [Wed, 13 Nov 2019 19:12:53 +0000 (11:12 -0800)]
docs: update calendar, add news item and link release notes for 19.2.4

5 years agodocs: Add SHA256 sum for for 19.2.4
Dylan Baker [Wed, 13 Nov 2019 19:09:32 +0000 (11:09 -0800)]
docs: Add SHA256 sum for for 19.2.4

5 years agodocs: Add release notes for 19.2.4
Dylan Baker [Wed, 13 Nov 2019 18:38:40 +0000 (10:38 -0800)]
docs: Add release notes for 19.2.4

5 years agoci: Expand the freedreno blit skip regex to cover more cases.
Eric Anholt [Wed, 13 Nov 2019 17:40:27 +0000 (09:40 -0800)]
ci: Expand the freedreno blit skip regex to cover more cases.

We've had flaps on at least:
- r16f_to_r16f
- r16i_to_rg16i

Reviewed-by: Daniel Stone <daniels@collabora.com>
5 years agoanv: Initialize depth_bounds_test_enable when not explicitly set
Caio Marcelo de Oliveira Filho [Tue, 12 Nov 2019 18:42:09 +0000 (10:42 -0800)]
anv: Initialize depth_bounds_test_enable when not explicitly set

This was causing uninitialized value to end up propagated to the
3DSTATE_DEPTH_BOUNDS packet, leading to asserts on packet
building due to the value being greater than 1.

Fixes: 939ddccb7a5 ("anv: Add support for depth bounds testing.")
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
5 years agopan/midgard: Remove util/ra support
Alyssa Rosenzweig [Fri, 1 Nov 2019 02:25:05 +0000 (22:25 -0400)]
pan/midgard: Remove util/ra support

It's now unused, in favour of LCRA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Integrate LCRA
Alyssa Rosenzweig [Fri, 1 Nov 2019 20:46:38 +0000 (16:46 -0400)]
pan/midgard: Integrate LCRA

Pretty routine, we do have a hack to force swizzle alignment for !32-bit
for until we implement !32-bit the right way.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Implement linearly-constrained register allocation
Alyssa Rosenzweig [Sat, 19 Oct 2019 23:43:47 +0000 (19:43 -0400)]
pan/midgard: Implement linearly-constrained register allocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Add blend shader selection bits for MRT
Alyssa Rosenzweig [Tue, 12 Nov 2019 19:19:52 +0000 (14:19 -0500)]
pan/midgard: Add blend shader selection bits for MRT

This is less complicated than previously thought. Note we have no way of
specifying the work register count for blend shaders; it must be
strictly less than the work register count of the corresponding fragment
shader (which is fine since we force the fragment shader to report a
count of 16 with a blend shader as a major hack until we get register
pressure down for blend shaders).

TODO: pandecode the flags.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agodrm-shim: fix EOF case
Christian Gmeiner [Tue, 12 Nov 2019 11:46:20 +0000 (12:46 +0100)]
drm-shim: fix EOF case

Close input end of the pipe after data was written. Without this
fix I have seen a hang in sysfs_uevent_get(.., "OF_FULLNAME")
when key was not found.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoutil/android: fix android build errors
Tapani Pälli [Tue, 12 Nov 2019 11:45:54 +0000 (13:45 +0200)]
util/android: fix android build errors

Fixes: 9020f519 ("util/u_endian: Add error checks")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2078
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agogitlab-ci: build RADV on ARM64
Samuel Pitoiset [Tue, 12 Nov 2019 13:25:16 +0000 (14:25 +0100)]
gitlab-ci: build RADV on ARM64

The ARMHF LLVM package is LLVM 7 but RADV requires LLVM 8.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agogitlab-ci: build a specific libdrm version for ARM64
Samuel Pitoiset [Tue, 12 Nov 2019 13:56:35 +0000 (14:56 +0100)]
gitlab-ci: build a specific libdrm version for ARM64

RADV requires libdrm-2.4.100 but the distrib package is too old.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agozink: move drawing separate source
Erik Faye-Lund [Wed, 6 Nov 2019 14:46:16 +0000 (15:46 +0100)]
zink: move drawing separate source

This code is kinda stand-alone, and it makes it a bit easier to find the
right source in the source-tree.

5 years agozink: move blitting to separate source
Erik Faye-Lund [Wed, 6 Nov 2019 14:36:43 +0000 (15:36 +0100)]
zink: move blitting to separate source

This code is kinda stand-alone, and it makes it a bit easier to find the
right source in the source-tree

5 years agozink: move filter-helper to separate helper-header
Erik Faye-Lund [Wed, 6 Nov 2019 14:36:43 +0000 (15:36 +0100)]
zink: move filter-helper to separate helper-header

This will help code-reuse a bit in the next commit.

5 years agozink: move format-checking to separate source
Erik Faye-Lund [Wed, 6 Nov 2019 14:26:12 +0000 (15:26 +0100)]
zink: move format-checking to separate source

This code is more or less stand-alone, and this keeps the formats array
a bit more encapsulated.

5 years agoci: Disable flappy blit tests on a630.
Eric Anholt [Tue, 12 Nov 2019 22:01:58 +0000 (14:01 -0800)]
ci: Disable flappy blit tests on a630.

These have shown up with the new CTS runner, which has changed test
ordering.

Reviewed-by: Daniel Stone <daniels@collabora.com>
5 years agofreedreno/ir3: remove unused parameter
Rob Clark [Tue, 12 Nov 2019 21:54:22 +0000 (13:54 -0800)]
freedreno/ir3: remove unused parameter

Signed-off-by: Rob Clark <robdclark@chromium.org>
5 years agofreedreno/ir3: legalize cleanups
Rob Clark [Sun, 10 Nov 2019 18:49:59 +0000 (10:49 -0800)]
freedreno/ir3: legalize cleanups

We can clear the "needs" flags once we emit a flag.  And also, don't
open-code the opcode name.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: fix gpu hang with pre-fs-tex-fetch
Rob Clark [Fri, 8 Nov 2019 20:55:27 +0000 (12:55 -0800)]
freedreno/ir3: fix gpu hang with pre-fs-tex-fetch

For pre-fs-dispatch texture fetch, we need to assign bary_ij to r0.x,
even if it is not used in the shader (ie. only varying use is for tex
coords).  But if, for example, gl_FragCoord is used, it could get
assigned on top of bary_ij, resulting in a GPU hang.

The solution to this is two-fold: (1) the inputs/outputs rework has the
benefit of making RA realize bary_ij is a vec2, even if there are no
split/collect instructions (due to no varying fetches in the shader
itself).  And (2) extend the live ranges of meta:input instructions to
the first non-input, to prevent RA from assigning the same register to
multiple inputs.

Backport note: because of (1) above, a better solution for 19.3 would be
to revert f30c256ec05.

Fixes: f30c256ec05 ("freedreno/ir3: enable pre-fs texture fetch for a6xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: only tex instructions have wrmask
Rob Clark [Fri, 1 Nov 2019 22:17:22 +0000 (15:17 -0700)]
freedreno/ir3: only tex instructions have wrmask

At the ir3 level, we would assume that we could use wrmask to mask
off other components of an instruction returning a vecN when they are
not used.  Which would let RA use components not written for other live
values.  But this is only true for tex instructions.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: re-work shader inputs/outputs
Rob Clark [Fri, 25 Oct 2019 22:37:56 +0000 (15:37 -0700)]
freedreno/ir3: re-work shader inputs/outputs

Allow inputs/outputs to be vecN (ie. whatever their actual size is), and
use split to get scalar components of inputs, and collect to gather up
scalar components of outputs.

The main motivation is to simplify RA, by only having to consider split/
collect to figure out where values need to land in consecutive scalar
registers, rather than having to also deal with left/right neighbors.

Because of varying packing, and the resulting fractional location
(location_frac), to implement load_input/store_output, it is still
convenient to have a table of scalar inputs/outputs.  We move this to
the compile ctx (since it is only needed for nir->ir3).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: simplify creating sysval inputs
Rob Clark [Fri, 25 Oct 2019 17:48:22 +0000 (10:48 -0700)]
freedreno/ir3: simplify creating sysval inputs

In almost all places, the add_sysval_input() is paired directly with a
create_input().  (The one exception is frag shader ij bary coord, and
this exception will go away in a later patch.)

So go ahead and clean this up before reworking input/output handling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: remove first-vertex sysval
Rob Clark [Fri, 25 Oct 2019 17:36:36 +0000 (10:36 -0700)]
freedreno/ir3: remove first-vertex sysval

This is a driver-param (loaded from uniform), not a sysval (populated by
hw into a register).  So it has no value to having a sysval slot.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: helper to print ir if debug enabled
Rob Clark [Fri, 25 Oct 2019 16:28:54 +0000 (09:28 -0700)]
freedreno/ir3: helper to print ir if debug enabled

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: show input/output wrmask's in disasm
Rob Clark [Fri, 25 Oct 2019 23:15:10 +0000 (16:15 -0700)]
freedreno/ir3: show input/output wrmask's in disasm

Currently it is always 0x1 (scalar), but that will change in a later
patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: add input/output iterators
Rob Clark [Thu, 24 Oct 2019 19:05:56 +0000 (12:05 -0700)]
freedreno/ir3: add input/output iterators

We can at least get rid of the if-not-NULL check in a bunch of places.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: remove impossible condition
Rob Clark [Sat, 26 Oct 2019 17:47:21 +0000 (10:47 -0700)]
freedreno/ir3: remove impossible condition

We keep kill's alive w/ keeps these days, rather than a fake output.
This condition was left over from prior to that change.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: rename fanin/fanout to collect/split
Rob Clark [Thu, 24 Oct 2019 17:22:33 +0000 (10:22 -0700)]
freedreno/ir3: rename fanin/fanout to collect/split

If I'm going to refactor a bit to use these meta instructions to also
handle input/output, then might as well cleanup the names first.
Nouveau also uses collect/split for names of these meta instructions,
and I like those names better.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: remove half-precision output
Rob Clark [Thu, 24 Oct 2019 18:26:34 +0000 (11:26 -0700)]
freedreno/ir3: remove half-precision output

This doesn't really work, we can't necessarily just change the outputs
to half-precision like this in anything but simple cases.

Keep the shader key entry around though, eventually with proper mediump
support we could use this with a nir pass to use lower precision frag
shader outputs when the render target format has <= 16b/component.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agofreedreno/ir3: fix valgrind complaint with STLW
Rob Clark [Sat, 9 Nov 2019 19:07:33 +0000 (11:07 -0800)]
freedreno/ir3: fix valgrind complaint with STLW

The instruction has 3 src regs, so `instr->regs[0..3]` are valid, but
`instr->regs[4]` is not.

```
Test case 'dEQP-GLES31.functional.shaders.linkage.es31.tessellation.varying.rules.output_superfluous_declaration'..
==29239== Invalid read of size 8
==29239==    at 0x5BE9CDC: emit_cat6 (ir3.c:841)
==29239==    by 0x5BEA1BF: ir3_assemble (ir3.c:921)
==29239==    by 0x5BDF0A7: ir3_shader_assemble (ir3_shader.c:133)
==29239==    by 0x5BDF193: assemble_variant (ir3_shader.c:162)
==29239==    by 0x5BDF407: create_variant (ir3_shader.c:215)
==29239==    by 0x5BDF4DB: shader_variant (ir3_shader.c:241)
==29239==    by 0x5BDF553: ir3_shader_get_variant (ir3_shader.c:257)
==29239==    by 0x5BA85F7: ir3_shader_variant (ir3_gallium.c:80)
==29239==    by 0x5BA7703: ir3_cache_lookup (ir3_cache.c:96)
==29239==    by 0x5B8B8B3: fd6_emit_get_prog (fd6_emit.h:119)
==29239==    by 0x5B8C137: fd6_draw_vbo (fd6_draw.c:186)
==29239==    by 0x5BB1FBB: fd_draw_vbo (freedreno_draw.c:290)
==29239==  Address 0xb97f2d0 is 0 bytes after a block of size 240 alloc'd
==29239==    at 0x4848D54: malloc (in /usr/lib/aarch64-linux-gnu/valgrind/vgpreload_memcheck-arm64-linux.so)
==29239==    by 0x61BD35B: ralloc_size (ralloc.c:119)
==29239==    by 0x61BD41B: rzalloc_size (ralloc.c:151)
==29239==    by 0x5BE599B: ir3_alloc (ir3.c:45)
==29239==    by 0x5BEA583: instr_create (ir3.c:984)
==29239==    by 0x5BEA5DF: ir3_instr_create2 (ir3.c:1000)
==29239==    by 0x5BEE317: ir3_STLW (ir3.h:1431)
==29239==    by 0x5BF12D3: emit_intrinsic_store_shared_ir3 (ir3_compiler_nir.c:903)
==29239==    by 0x5BF418B: emit_intrinsic (ir3_compiler_nir.c:1802)
==29239==    by 0x5BF5D07: emit_instr (ir3_compiler_nir.c:2339)
==29239==    by 0x5BF603F: emit_block (ir3_compiler_nir.c:2426)
==29239==    by 0x5BF624B: emit_cf_list (ir3_compiler_nir.c:2474)
==29239==
```

Probably this only triggers in non-optimized builds?

Fixes: 1f3b52ce503 ("freedreno/a6xx: Add register offset for STG/LDG")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agoci: Remove old commented copy of freedreno artifacts.
Eric Anholt [Tue, 12 Nov 2019 19:50:43 +0000 (11:50 -0800)]
ci: Remove old commented copy of freedreno artifacts.

This path was from an older version of freedreno CI.

5 years agoci: Enable all of GLES3/3.1 testing for softpipe.
Eric Anholt [Tue, 5 Nov 2019 18:31:29 +0000 (10:31 -0800)]
ci: Enable all of GLES3/3.1 testing for softpipe.

Now that we're not using so many job slots, it's easy to get these
jobs run in a reasonable amount of time (gles3 took 10 minutes for 4
cores, and gles31 was 15 minutes for 4 cores).

Acked-by: Michel Dänzer <mdaenzer@redhat.com>
5 years agoci: Use cts_runner for our dEQP runs.
Eric Anholt [Mon, 4 Nov 2019 18:54:41 +0000 (10:54 -0800)]
ci: Use cts_runner for our dEQP runs.

This runner is a little project by Bas, written in C++, that spawns
threads that then loop grabbing chunks of the (randomly shuffled but
consistently so) test list and hand it to a dEQP instance.  As the
remaining list gets shorter, so do the chunks, so hopefully the
threads all complete effectively at once.  It also handles restarting
after crashes automatically.  I've extended the runner a bit to do
what I was doing in the bash scripts before, like the skip list and
expected failures handling.  This project should also be a good
baseline for extending to handle retesting of intermittent failures.

By switching to it, we can have the swrast tests just take up one job
slot on the shared runners and keep their allotment of CPUs busy,
instead of taking up job slots with single-threaded dEQP jobs.  It
will also let us (eventually, once I reprovision) switch the freedreno
runners over to threading within the job instead of running concurrent
jobs, so that memory scribbles in one pipeline don't affect unrelated
pipelines, and I can experiment with their parallelism (particularly
on a306 where we are frequently backed up) without trashing other
people's jobs.

What we lose in this process is per-test output in the log (not a big
loss, I think, since we summarize fails at the end and reducing log
length keeps chrome from choking on our logs so badly).  We also drop
the renderer sanity checking, since it's not saving qpa files for us
to go poke through.  Given that all the drivers involved have fail
lists, if we got the wrong renderer somehow, we'd get a job failure
anyway.

v2: Rebase on droppong of the autoscale cluster and the arm64
    build/test split.  Use a script to deduplicate the cts-runner
    build.
v3: Rebase on the amd64 build/test container split.

Acked-by: Daniel Stone <daniels@collabora.com> (v1)
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> (v2)
5 years agoci: Make the skip list regexes match the full test name.
Eric Anholt [Tue, 5 Nov 2019 17:50:40 +0000 (09:50 -0800)]
ci: Make the skip list regexes match the full test name.

The bash scripts were using grep in the manner that matches any subset
of the line, but the new CTS runner matches the whole line and I think
that's a pretty good behavior.  Given that some of the skip lists
already were written to match the full test name, just make them
consistently do so.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
5 years agoci: Use several debian buster packages instead of hand-building.
Eric Anholt [Mon, 4 Nov 2019 19:05:25 +0000 (11:05 -0800)]
ci: Use several debian buster packages instead of hand-building.

This helps cut down our container build time.  I've left a few that
we're likely to rev more frequently or I was less confident in
dropping.

v2: Rebase on the build/test container split, now bumps the build
    container tag in this commit.

Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Acked-by: Daniel Stone <daniels@collabora.com> (v1)
5 years agoiris: Use mocs from isl_dev.
Rafael Antognolli [Tue, 5 Nov 2019 23:08:01 +0000 (15:08 -0800)]
iris: Use mocs from isl_dev.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Use mocs settings from isl_dev.
Rafael Antognolli [Tue, 5 Nov 2019 19:12:36 +0000 (11:12 -0800)]
anv: Use mocs settings from isl_dev.

v2: Remove device->default_mocs and external_mocs (Jason).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/isl: Add MOCS settings to isl_device.
Rafael Antognolli [Tue, 5 Nov 2019 19:11:53 +0000 (11:11 -0800)]
intel/isl: Add MOCS settings to isl_device.

Centralize mocs settings into isl.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agofreedreno: fix eglDupNativeFenceFD error
Rob Clark [Tue, 12 Nov 2019 17:01:34 +0000 (09:01 -0800)]
freedreno: fix eglDupNativeFenceFD error

We can end up with scenarios where last_fence is associated with a batch
that is flushed through some other path before needs_out_fence_fd gets
set.  Resulting in returning a fence that has no backing fd.

The simplest thing is to just skip the optimization to try and avoid
no-op batches when a fence-fd is requested.  This should normally be
just once a frame anyways.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agonir: fix a couple signed/unsigned comparison warnings in nir_builder.h
Brian Paul [Mon, 11 Nov 2019 23:43:45 +0000 (16:43 -0700)]
nir: fix a couple signed/unsigned comparison warnings in nir_builder.h

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agos/APIENTRY/GLAPIENTRY/ in teximage.c
Brian Paul [Mon, 11 Nov 2019 23:22:49 +0000 (16:22 -0700)]
s/APIENTRY/GLAPIENTRY/ in teximage.c

The later is the right symbol for entrypoint functions.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoandroid: mesa: Revert "android: mesa: revert "Enable asm unconditionally""
Lepton Wu [Wed, 30 Oct 2019 00:41:14 +0000 (17:41 -0700)]
android: mesa: Revert "android: mesa: revert "Enable asm unconditionally""

Commit 45206d7673adb1484cbdb3eadaf82e0849c9cdcf fixed PIC issue of x86 asm stub.
We can enable asm for Android x86 now. This should sightly improve performance.

Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lepton Wu <lepton@chromium.org>
5 years agoaco: combine read_invocation and shuffle implementations
Rhys Perry [Tue, 12 Nov 2019 15:55:05 +0000 (15:55 +0000)]
aco: combine read_invocation and shuffle implementations

They do mostly the same thing now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: don't propagate vgprs into v_readlane/v_writelane
Rhys Perry [Tue, 12 Nov 2019 15:53:15 +0000 (15:53 +0000)]
aco: don't propagate vgprs into v_readlane/v_writelane

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
5 years agoaco: fix read_invocation with VGPR lane index
Rhys Perry [Tue, 12 Nov 2019 15:44:17 +0000 (15:44 +0000)]
aco: fix read_invocation with VGPR lane index

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
5 years agonir/divergence: improve DA of shuffle
Rhys Perry [Tue, 12 Nov 2019 15:29:45 +0000 (15:29 +0000)]
nir/divergence: improve DA of shuffle

If the data is uniform, then it's really a uniform copy. If the index is
uniform, then it's really a read_invocation.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agoaco: fix shuffle with uniform operands
Rhys Perry [Tue, 12 Nov 2019 15:28:52 +0000 (15:28 +0000)]
aco: fix shuffle with uniform operands

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
5 years agoaco: use DPP instead of exec modification when lowering GFX10 shuffles
Rhys Perry [Tue, 12 Nov 2019 15:00:48 +0000 (15:00 +0000)]
aco: use DPP instead of exec modification when lowering GFX10 shuffles

Seems we can use DPP's row_mask field to get an effect similar to
modifying exec.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
5 years agogitlab-ci: build libdrm using meson instead of autotools
Eric Engestrom [Tue, 12 Nov 2019 14:29:44 +0000 (14:29 +0000)]
gitlab-ci: build libdrm using meson instead of autotools

Autotools was deprecated for a while and has now been removed, so let's
start using meson here so that we won't have any issues next time we
update libdrm.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
5 years agoaco: rematerialize s_movk instructions
Daniel Schürmann [Wed, 6 Nov 2019 16:47:06 +0000 (17:47 +0100)]
aco: rematerialize s_movk instructions

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agoaco: preserve kill flag on moved operands during RA
Daniel Schürmann [Thu, 7 Nov 2019 15:22:55 +0000 (16:22 +0100)]
aco: preserve kill flag on moved operands during RA

Fixes: 93c8ebfa780ebd1495095e794731881aef29e7d3 aco: Initial commit of independent AMD compiler
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agoaco: fix invalid access on Pseudo_instructions
Daniel Schürmann [Fri, 8 Nov 2019 15:36:11 +0000 (16:36 +0100)]
aco: fix invalid access on Pseudo_instructions

Fixes: 93c8ebfa780ebd1495095e794731881aef29e7d3 aco: Initial commit of independent AMD compiler
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
5 years agozink: remove no-longer-needed hack
Erik Faye-Lund [Thu, 7 Nov 2019 16:48:32 +0000 (17:48 +0100)]
zink: remove no-longer-needed hack

It seems whatever was causing this is no longer an issue. So let's get
rid of the hack here.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
5 years agozink: implement buffer-to-buffer copies
Erik Faye-Lund [Fri, 8 Nov 2019 11:53:43 +0000 (12:53 +0100)]
zink: implement buffer-to-buffer copies

5 years agozink: always allow transfer to/from buffers
Erik Faye-Lund [Fri, 8 Nov 2019 11:54:09 +0000 (12:54 +0100)]
zink: always allow transfer to/from buffers

5 years agointel/blorp: Fix usage of uninitialized memory in key hashing
Danylo Piliaiev [Wed, 30 Oct 2019 14:14:06 +0000 (16:14 +0200)]
intel/blorp: Fix usage of uninitialized memory in key hashing

The automatically generated padding in structs contains
undefined values, force pack the structs to eliminate the
padding. Otherwise structs with the same values may generate
different hashes.

Valgrind output:

Conditional jump or move depends on uninitialised value(s)
 util_fast_urem32 (fast_urem_by_const.h:71)
 hash_table_search (hash_table.c:262)
 _mesa_hash_table_search (hash_table.c:296)
 anv_pipeline_cache_search_locked (anv_pipeline_cache.c:318)
 anv_pipeline_cache_search (anv_pipeline_cache.c:335)
 lookup_blorp_shader (anv_blorp.c:38)
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1112)
 blorp_mcs_partial_resolve (blorp_clear.c:1205)
 anv_image_mcs_op (anv_blorp.c:1742)
 anv_cmd_predicated_mcs_resolve (genX_cmd_buffer.c:774)
 transition_color_buffer (genX_cmd_buffer.c:1159)
 cmd_buffer_end_subpass (genX_cmd_buffer.c:4840)

Uninitialised value was created by a stack allocation
 blorp_params_get_mcs_partial_resolve_kernel (blorp_clear.c:1103)

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoi965/program_cache: Lift restriction on shader key size
Danylo Piliaiev [Fri, 8 Nov 2019 15:47:57 +0000 (17:47 +0200)]
i965/program_cache: Lift restriction on shader key size

This will allow usage of packed structs which may have size
not divisible by 4.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agogitlab-ci: Delete install/bin from artifacts as well
Michel Dänzer [Wed, 6 Nov 2019 18:58:19 +0000 (19:58 +0100)]
gitlab-ci: Delete install/bin from artifacts as well

This cuts the x86 artifacts zip file size in less than half.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Use separate docker images for x86 build/test jobs
Michel Dänzer [Tue, 5 Nov 2019 17:52:24 +0000 (18:52 +0100)]
gitlab-ci: Use separate docker images for x86 build/test jobs

Same as was done for the ARM images before.

This should make it less painful to update to newer dEQP / piglit as
well as to make changes to the build/test environment.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Run piglit tests with llvmpipe
Michel Dänzer [Tue, 22 Oct 2019 15:16:52 +0000 (17:16 +0200)]
gitlab-ci: Run piglit tests with llvmpipe

One job for the quick_gl profile, one for the glslparser & quick_shader
profiles (doing these together takes hardly any more time than
quick_shader alone).

v2:
* Don't break lava tests
v3:
* Remove piglit test artifacts paths:
* Exclude some quick_shader tests again:
  - Test whose result flips between pass/fail/skip
  - *@vs_in tests, as not the same one of these gets picked every time
v4:
* Do not list passing tests in .gitlab-ci/piglit/*.txt (Eric Anholt)
* Include the test number summary in .gitlab-ci/piglit/*.txt
* Completely disable generating any vs_in tests in the piglit build.
* Remove some more unneded files from the piglit build tree.
* Exclude quick_gl arb_gpu_shader5 tests; they were all skipped anyway,
  as llvmpipe doesn't support this extension yet, but occasionally they
  would spuriously fail instead.
v5:
* Set LD_LIBRARY_PATH, so we actually test the Mesa build from the
  pipeline...
* Verify that wflinfo reports the expected Mesa version
* Pass -noreset to Xvfb
v6:
* Don't use autoscale runners, run piglit with -j4 (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Sort packages in debian-install.sh
Michel Dänzer [Wed, 6 Nov 2019 16:05:56 +0000 (17:05 +0100)]
gitlab-ci: Sort packages in debian-install.sh

And remove duplicates.

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Share dEQP build process between x86 & ARM test image scripts
Michel Dänzer [Tue, 5 Nov 2019 18:02:17 +0000 (19:02 +0100)]
gitlab-ci: Share dEQP build process between x86 & ARM test image scripts

See https://gitlab.freedesktop.org/mesa/mesa/issues/2056

v2:
* Rename .gitlab-ci/deqp-build.sh => .gitlab-ci/build-deqp.sh
  (Eric Anholt)

Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Move artifact preparation to separate script
Michel Dänzer [Wed, 23 Oct 2019 16:42:53 +0000 (18:42 +0200)]
gitlab-ci: Move artifact preparation to separate script

It's currently only needed for the meson-main and meson-arm64 jobs, not
the other meson build jobs.

Also remove MESON_SHADERDB, just run .gitlab-ci/run-shader-db.sh
directly from the meson-main job.

v2:
* Also run prepare-artifacts.sh in meson-arm64 script
v3:
* Move tarball creation into the new script as well, as it prevented
  ccache --show-stats from running in after_script

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> # v1
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agogitlab-ci: Use ninja -j4 for building dEQP
Michel Dänzer [Tue, 22 Oct 2019 16:27:53 +0000 (18:27 +0200)]
gitlab-ci: Use ninja -j4 for building dEQP

By default, ninja tries to saturate all cores of the runner host
machine, which could overload it due to other jobs running in parallel.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agospirv: Fix the MSVC build
Jason Ekstrand [Mon, 11 Nov 2019 15:37:50 +0000 (09:37 -0600)]
spirv: Fix the MSVC build

Fixes: 9cc4c2c91649b "spirv: Add a vtn_decorate_pointer helper"
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agonir: patch up deref-vars when lowering clip-planes
Erik Faye-Lund [Wed, 30 Oct 2019 13:53:56 +0000 (14:53 +0100)]
nir: patch up deref-vars when lowering clip-planes

Otherwise, we fail validation and potentially generate invalid code.
Let's fix up the mode of the accesses to the variable.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoac: handle pointer types to LDS in ac_get_elem_bits()
Samuel Pitoiset [Mon, 11 Nov 2019 10:34:05 +0000 (11:34 +0100)]
ac: handle pointer types to LDS in ac_get_elem_bits()

This fixes crashes with some
dEQP-VK.spirv_assembly.instruction.spirv1p4.* tests.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agofreedreno: add Adreno 640 ID
Jonathan Marek [Thu, 7 Nov 2019 12:28:37 +0000 (07:28 -0500)]
freedreno: add Adreno 640 ID

A640 seems to work without any other changes (glmark and vkcube).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
5 years agoradv: fix radv secure compile feature breaks compilation on armhf EABI and aarch64
Luis Mendes [Sat, 9 Nov 2019 23:21:05 +0000 (23:21 +0000)]
radv: fix radv secure compile feature breaks compilation on armhf EABI and aarch64

__NR_select is not defined the same way across architectures, sometimes is
not even defined, like in armhf EABI and aarch64.

Signed-off-by: Luis Mendes <luis.p.mendes@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2042
5 years agost/mesa: remove unused TGSI-only debug printing functions
Marek Olšák [Sat, 9 Nov 2019 00:43:10 +0000 (19:43 -0500)]
st/mesa: remove unused TGSI-only debug printing functions

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agost/mesa: add ST_DEBUG=nir to print NIR shaders
Marek Olšák [Sat, 9 Nov 2019 00:40:44 +0000 (19:40 -0500)]
st/mesa: add ST_DEBUG=nir to print NIR shaders

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agost/mesa: print TCS/TES/GS/CS TGSI in the right place & keep disk cache enabled
Marek Olšák [Sat, 9 Nov 2019 00:35:02 +0000 (19:35 -0500)]
st/mesa: print TCS/TES/GS/CS TGSI in the right place & keep disk cache enabled

The old place only printed on a disk cache miss, which is why the disk
cache was disabled.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
5 years agost/mesa: remove \n being only printed in debug builds after printed TGSI
Marek Olšák [Sat, 9 Nov 2019 00:32:25 +0000 (19:32 -0500)]
st/mesa: remove \n being only printed in debug builds after printed TGSI

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>