Gabe Black [Tue, 7 Aug 2018 08:26:14 +0000 (01:26 -0700)]
systemc: Fix the seed used with sc_gen_unique_name for sc_port.
The seed should only be "port" not "sc_port".
Change-Id: Ia046103abc0a9ed283fcb7cf7d8069383a1e2b0d
Reviewed-on: https://gem5-review.googlesource.com/12067
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 7 Aug 2018 08:23:01 +0000 (01:23 -0700)]
systemc: Implement sc_gen_unique_name.
The Accellera implementation statically allocates the buffer it uses to
build the unique names and only allocates the name generator if it's
going to be used for a particular module. I assume that's to avoid
allocating a large buffer if it's not going to be used.
In this implementation, I use an std::string which manages its own
memory and so shouldn't need to be selectively allocated. I also use a
string stream to construct the name instead of sprintf.
Change-Id: If92c68586a85b5d27c067a75a6e9ebbf00d8c785
Reviewed-on: https://gem5-review.googlesource.com/12066
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 08:49:52 +0000 (01:49 -0700)]
systemc: Always set USE_SYSTEMC=1 when compiling with verify.py.
It doesn't make sense not to have systemc enabled when building the
systemc regression tests.
Change-Id: I23b81fd4d7cbd0dbf5efbea773d816296d6492be
Reviewed-on: https://gem5-review.googlesource.com/12065
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 08:13:23 +0000 (01:13 -0700)]
systemc: Make verify.py ignore an Info: message.
This message is about how to disable a warning about sc_bit being
deprecated.
Change-Id: I1a0b12e2ca5b58328e37605ba3f7e3e1a384e351
Reviewed-on: https://gem5-review.googlesource.com/12064
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 08:07:15 +0000 (01:07 -0700)]
systemc: Adjust a warning to match Accellera.
This is to pass fix a diff in the regression tests.
Change-Id: Id1b963df647224d7a3589febe7986353a4a8e440
Reviewed-on: https://gem5-review.googlesource.com/12063
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Brandon Potter [Wed, 18 Apr 2018 18:45:37 +0000 (14:45 -0400)]
syscall_emul: implement dir-related syscalls
Add getdents, rmdir, chdir, and mknod to SE mode for x86.
Change-Id: I387ea3066869e8999bc0064f74070f4e47c1e9a1
Reviewed-on: https://gem5-review.googlesource.com/12112
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Brandon Potter [Wed, 18 Apr 2018 18:44:10 +0000 (14:44 -0400)]
syscall_emul: refactor FDEntry and children classes
Strips off superfluous inline specifiers in header file.
Changes return types and parameters that deal with strings
to include the const& specifiers.
Change-Id: I570b1801abb059b91216f0223458d00963b9ca1c
Reviewed-on: https://gem5-review.googlesource.com/12111
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Brandon Potter [Wed, 18 Apr 2018 18:42:31 +0000 (14:42 -0400)]
syscall_emul: style changes and FDArray refactor
Some members were defined as public when they should have been
privately declared so these were moved to the appropriate spot.
The operator[] had inline specified for for an in-class
definition which is redundant since inline definitions are
always implicitly inline.
Private members had the leading underscore applied to them to
denote that they're private (consistent with style guide).
Changed static const defined class variable into a constexpr
with brace-list initialization.
Change-Id: If3054416b57827d1542e9ebab428d67d0e767723
Reviewed-on: https://gem5-review.googlesource.com/12110
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Brandon Potter [Fri, 4 May 2018 21:55:24 +0000 (17:55 -0400)]
syscall_emul: expand AuxVector class
The AuxVector class is responsible for holding Process data.
The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is
to pass in information that the process will need for various
reasons. (Check out the enum in the header file for an idea of
what the AuxVector holds.)
The AuxVector struct was changed into a class and encapsulation
methods were added to protect access to the member variables.
The host ISA may have a different endianness than the simulated
ISA. Since data is passed between the process address space and
the simulator for auxiliary vectors, we need to worry about
maintaining endianness for the right context.
Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9
Reviewed-on: https://gem5-review.googlesource.com/12109
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Ciro Santilli [Fri, 31 Aug 2018 10:39:19 +0000 (11:39 +0100)]
scons: remove as version check
GNU as 2.31.1 checks if the input and output files are the same:
Assembler messages:
Fatal error: The input and output files must be distinct
The check already does not work for llvm-as which has a different
output format.
Since it is too hard to maintain the check correctly for all possible
assemblers, it is better to just remove it completely.
Change-Id: I38a993ab83ca83d4a2f5e77820d2ca903f70c6ac
Reviewed-on: https://gem5-review.googlesource.com/12403
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Wed, 19 Sep 2018 08:19:06 +0000 (10:19 +0200)]
mem-cache: Fix non-bijective function in Skewed caches
The hash() function must be bijective for the skewed caches to work,
however when the hashing is done on top of a one-bit address, the
MSB and LSB refer to the same bit, and therefore their xor will
always be zero.
This patch adds a fatal error to not allow the user to set an invalid
value for the number of sets that would generate that bug.
As a side note, the missing header for the bitfields functions has
been added.
Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021
Reviewed-on: https://gem5-review.googlesource.com/12724
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maurice Becker [Tue, 18 Sep 2018 08:14:24 +0000 (10:14 +0200)]
dev, arm: fix error class-memaccess with GCC >= 8.1
From GCC 8.1 on GCC issues a warning when using memset et al on structs and
classes. With the way gem5 builds, this actually prevents successful
builds.
Instead of using a pointer with SCSIReply as type, we cast to a void
pointer to avoid the message. On the way we wrap the memset call into a
method of SCSIReply called reset for better code readability.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: I3ed3fd9714be5d253aba01ca00b1863e1ae5cb68
Reviewed-on: https://gem5-review.googlesource.com/12685
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maurice Becker [Tue, 18 Sep 2018 08:27:40 +0000 (10:27 +0200)]
Pl011: Added registers UART_RSR/UART_ECR
UART_RSR shows errors with the transmission and UART_ECR can clear
those (according to PL011 Technical Reference Manual Revision r1p4). As
these transmission errors never occur, they are implemented as RAZ/WI.
Both registers exist at the same offset 0x004. RSR is read-only, ECR is
write-only.
Signed-off-by: Maurice Becker <madnaurice@googlemail.com>
Change-Id: Ia9d13c90c65feccf3ecec36a782170755b1e1c02
Reviewed-on: https://gem5-review.googlesource.com/12686
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 17 Aug 2018 09:17:59 +0000 (10:17 +0100)]
mem: Implement QoS Proportional Fair policy
Providing a configurable fair scheduling policy based on utilization;
utilization is directly proportional to a score which is inversely
proportional to the QoS priority. It is meant to avoid starvation of low
priority packets.
Users can tune the policy by adjusting the weight parameter (weight of
the following formula)
new_score = ((1.0 - weight) * old_score) + (weight * served_bytes)
Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12359
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Sherif Elhabbal [Fri, 14 Sep 2018 15:10:24 +0000 (17:10 +0200)]
config, arm, power: Example to report the power for the L2 Cache
This patch add an example to demonstrate how to report the power for the L2
Cache of the big cluster separately ,it decouples the L2 contributions from
the CPU power equation
Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Idde43c8bcb10df9d44d20282eaf21ce87a9d3f58
Reviewed-on: https://gem5-review.googlesource.com/12684
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Sherif Elhabbal [Thu, 13 Sep 2018 14:01:55 +0000 (16:01 +0200)]
power: Add a clock_period variable to power expressions
Currently 'Clock period in ticks' stat is not accessible in power equations .
This patch adds a variable 'clock_period' to be referenced to get the Clock period in
ticks
Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com>
Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72
Reviewed-on: https://gem5-review.googlesource.com/12664
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Earl Ou [Fri, 7 Sep 2018 07:16:53 +0000 (15:16 +0800)]
Fix SConstruct for asan build
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes
some build error when using --with-asan.
Bug: None
Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug
Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7
Reviewed-on: https://gem5-review.googlesource.com/12511
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Anouk Van Laer [Tue, 4 Sep 2018 10:44:42 +0000 (11:44 +0100)]
arch-arm: Correction for address size in EL1&0 translation
When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).
See D10.2.121 of the ARM ARM.
Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Anouk Van Laer [Mon, 3 Sep 2018 10:18:31 +0000 (11:18 +0100)]
arch-arm: Correction to address size in EL2/EL3
This commit corrects how the address size is
determined in EL2/EL3. Previously, TCR_ELx.ips
was used but this should be TCR_ELx.ps.
Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12551
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Nikos Nikoleris [Sat, 1 Sep 2018 14:38:13 +0000 (15:38 +0100)]
mem-cache: Fix bug in handleAtomicReqMiss
"
4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.
Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Ciro Santilli [Wed, 12 Sep 2018 14:33:01 +0000 (15:33 +0100)]
dev-arm: fix build to missing Pl390 to Gicv2 rename
Change-Id: I6756f2c789aaca410d201aa64147443b66afee39
Reviewed-on: https://gem5-review.googlesource.com/12645
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ciro Santilli [Thu, 30 Aug 2018 09:58:10 +0000 (10:58 +0100)]
config, dev-arm: Fix UART handling baremetal mode
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform
due to inconsistent UART naming with error message:
AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'
Consistently name keep all UARTs in the Arm platforms in a vector named
'uart' or as a single device named 'uart'. Update the configuration
scripts to reflect the fact that 'uart' can be a vector.
Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12473
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ciro Santilli [Thu, 30 Aug 2018 13:50:31 +0000 (14:50 +0100)]
dev-arm: rename Pl390 to GicV2
The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.
GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.
Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ciro Santilli [Thu, 30 Aug 2018 13:50:31 +0000 (14:50 +0100)]
dev-arm: improve Pl390 parameters
Remove default dist_addr and cpu_addr register addresses since those are
purely platform specific.
Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and
distributor base too close for the newer CPU size of 0x2000, leading to
overlap.
This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes
using RealViewPBX fail with:
fatal: system.membus has two ports responding within range
[0x1f000100 : 0x1f0020ff]:
system.realview.gic.pio
system.realview.gic.pio
Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Tue, 15 Mar 2016 15:45:12 +0000 (15:45 +0000)]
cpu: Replace the fastmem with a new CPU model
The AtomicSimpleCPU used to be able to access memory directly to speed
up simulation if no caches are used. This is fine as long as no
switching between CPU models is required. In order to switch to a new
CPU model that requires caches, we currently need to checkpoint the
system and restore it into a new configuration. The new
'atomic_noncaching' memory mode provides a solution that avoids this
issue since caches are bypassed in this mode. This changeset removes
the old fastmem option from the AtomicSimpleCPU and introduces a new
CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU
used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests
switching between a NonCachingSimpleCPU and a TimingSimpleCPU with
caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12419
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Sat, 28 Jul 2018 07:57:55 +0000 (00:57 -0700)]
systemc: Adjust some whitespace in a print out.
This makes a test output file diff successfully.
Change-Id: Ia269b4b33f719a2559197d9296f9acc601ec65f7
Reviewed-on: https://gem5-review.googlesource.com/12062
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 07:14:41 +0000 (00:14 -0700)]
systemc: Make verify.py ignore another warning.
Also make warning filters more general and easier to add by writing a
function to generate them.
Change-Id: I8d813ded9ad8a9ccac4e48e5ea80a3c9c23959da
Reviewed-on: https://gem5-review.googlesource.com/12061
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 06:39:10 +0000 (23:39 -0700)]
systemc: Make verify.py compare non output log reference files.
There are only a few of these which are vcd files. If there are
reference files which aren't the log and which aren't in the gem5
output directory, mark those tests as failed as well.
Change-Id: I2c880c13d0f90ccf16ac0439dbac68de9223cc90
Reviewed-on: https://gem5-review.googlesource.com/12060
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 06:06:47 +0000 (23:06 -0700)]
systemc: Delete empty/misnamed test reference file.
The name of the reference file doesn't match the name of the test, and
is empty. There's also a correctly named log file in the same directory
which will be used instead.
Change-Id: I6501b465b99af403ae4af6d43189280c4b45fc8f
Reviewed-on: https://gem5-review.googlesource.com/12059
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 28 Jul 2018 06:01:55 +0000 (23:01 -0700)]
systemc: Remove some junk test reference files.
These files have truncated names, and are identical to correct versions
of the log files.
Change-Id: I1e5e3c8c489d41dea21f62b4664b05bf6a742117
Reviewed-on: https://gem5-review.googlesource.com/12058
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 27 Jul 2018 23:28:50 +0000 (16:28 -0700)]
systemc: Ensure the terminated event is notified in all cases.
The terminated event was being notified if a process was killed, but
not if it was terminated in other ways. This change moves the
notification into the helper which sets termination related state.
Change-Id: I10aa5ad25875db992c8408dc60f087efc76b336b
Reviewed-on: https://gem5-review.googlesource.com/12057
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 27 Jul 2018 23:06:32 +0000 (16:06 -0700)]
systemc: Make verify.py delete obsolete diff files.
If diff file exists but the underlying diff has been fixed, delete the
diff file.
Change-Id: Icadc21a61c084198a8a246ab6d00a9b885647cde
Reviewed-on: https://gem5-review.googlesource.com/12056
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 27 Jul 2018 23:04:31 +0000 (16:04 -0700)]
systemc: Make verify.py ignore a warning.
Change-Id: Ia887b7195d84d0ba9e77370d7b928e201ca78731
Reviewed-on: https://gem5-review.googlesource.com/12055
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 27 Jul 2018 10:32:22 +0000 (03:32 -0700)]
systemc: Teach verify.py to diff files when checking test results.
Currently it just diffs the stdout and ignores other reference files.
It also doesn't filter out noise in the diffs from non test related
simulator messages. These include startup messages, messages when the
simulator finishes executing, and some non-standard warnings, etc.
Change-Id: Idcb19edd893cd8818423c2c5ebb6cbfb278baffa
Reviewed-on: https://gem5-review.googlesource.com/12054
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 27 Jul 2018 00:53:01 +0000 (17:53 -0700)]
systemc: Add return code verification to verify.py.
This just checks whether gem5 exited of its own accord with a
successful error code, or in other words that it didn't hang or crash.
More checking will need to be added to verify the output against the
golden reference.
Change-Id: I1ddef56aa73b5f700743830bd6212804531c484f
Reviewed-on: https://gem5-review.googlesource.com/12053
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 26 Jul 2018 23:37:56 +0000 (16:37 -0700)]
systemc: Record the test's return code in the output directory.
verify.py will be able to use that value later to determine whether a
test was successful.
Change-Id: Ib499a4b6f202ee46e66e5de1b61a7e6309df9886
Reviewed-on: https://gem5-review.googlesource.com/12052
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 26 Jul 2018 23:06:01 +0000 (16:06 -0700)]
systemc: Extend the execute phase of verify.py.
Add -j and --timeout options to the execute phase of verify.py.
The --timeout option is implemented using the timeout utility program
which is assumed to be available on the host system. Python 3.3 added
a timeout argument to the subprocess module which is an alternative
approach, but then we would be dependent on python 3.3.
-j is implemented using the standard multiprocess.pool.ThreadPool
class.
Change-Id: I15b92f2b14de6710e2027a6a19984b2644b2a8df
Reviewed-on: https://gem5-review.googlesource.com/12051
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 26 Jul 2018 22:15:20 +0000 (15:15 -0700)]
systemc: Detect a process control corner case and report an error.
This error reporting results in an exception being thrown, and one (or
more) of the tests depend on that behavior.
Change-Id: I858aa14fbb80b0648392179a6a8d2055c91aedf8
Reviewed-on: https://gem5-review.googlesource.com/12050
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 26 Jul 2018 22:13:52 +0000 (15:13 -0700)]
systemc: Adjust process status tracking to improve kill/reset support.
This change rearranges how process status is tracked so that the kill
and reset mechanisms work in more circumstances and more like they're
supposed to according to the spec. This makes another test or two pass.
Change-Id: Ie2a683a796155a82092109d5bb45f07c84e06c76
Reviewed-on: https://gem5-review.googlesource.com/12049
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 26 Jul 2018 02:30:30 +0000 (19:30 -0700)]
systemc: Implement most of the sc_report_handler mechanism.
This doesn't include support for the deprecated integer message ids.
Change-Id: I309d58df1cdc464428189eb0b7180edf41ca4f67
Reviewed-on: https://gem5-review.googlesource.com/12048
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 24 Jul 2018 02:39:52 +0000 (19:39 -0700)]
systemc: Ignore direct requests to mark a process as ready.
That might happen when a process is being marked as ready at the start
of simulation.
Because the process might not end up on the ready list, displacing it
from the init list, excplicitly pop it off the init list as well.
Change-Id: Iebf972e3e1baedec17b9b99b4da9dd44cd8e6957
Reviewed-on: https://gem5-review.googlesource.com/12047
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 05:16:12 +0000 (22:16 -0700)]
systemc: Fill out process handle kill and reset mechanisms.
Some flags were being updated too early, making the functions think
what they were about to do had already been done. Also, actually check
for and throw the exception installed in a process when it's next
supposed to run, and when injecting an exception schedule that other
process to run immediately.
Change-Id: I0856b69903699b2c66f9dc7f44942bbfe3cfdcc4
Reviewed-on: https://gem5-review.googlesource.com/12046
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 05:13:14 +0000 (22:13 -0700)]
systemc: Fix a "problem" with kill/reset exceptions.
Despite what it says in the spec, the proc_ctrl compliance test throws
a copy of the reset exception it catches, not the original. Because of
that, the code in the kernel which catches the exception gets the base
class, not the derived class with overridden virtual methods, etc.
This happens to work for the Accellera implementation because they
manipulate members of the base class itself which are preserved despite
this bug. To make the test work, we imitate their implementation, even
though it exposes more implementation details through the header files.
Change-Id: I7ed9818c0552869ec790cb7f7bfbe365ade5e49c
Reviewed-on: https://gem5-review.googlesource.com/12045
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 02:27:27 +0000 (19:27 -0700)]
systemc: Implement much of sc_spawn.
This doesn't implement reset signals, although those aren't implemented
for static processes either yet.
Change-Id: I748a7f75b9b91774c91d969bc1ff5b07e1711aa3
Reviewed-on: https://gem5-review.googlesource.com/12044
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 02:25:48 +0000 (19:25 -0700)]
systemc: Promote some functions to sc_export_base.
There are a few functions which return a generic sc_interface pointer
which were (in the spec) defined to be in the interface type specific
sc_export class. They don't need to be and aren't in the Accellera
implementation, and without having them in the base class there's no
good way to get at a generic interface pointer from an export.
Change-Id: Iba692c79bf1d4f7684f28447d8b22c88ef4b804d
Reviewed-on: https://gem5-review.googlesource.com/12043
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 02:24:58 +0000 (19:24 -0700)]
systemc: Add a sensitivity type for exports.
Dynamic processes can be sensitive to exports, so we need a pending
sensitivity to represent them.
Change-Id: I87952f8bbb7847ad1f1d98d35cd5dd488e7b28ab
Reviewed-on: https://gem5-review.googlesource.com/12042
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 02:23:58 +0000 (19:23 -0700)]
systemc: Make some functions of the kernel static.
This makes it possible to call them without having to have a kernel
instance available. The kernel is a singleton anyway, so there should
only ever be a single instance of any of these values.
Change-Id: I3610d60cc72e9f3114997fe63db94b96ccaac3cd
Reviewed-on: https://gem5-review.googlesource.com/12041
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 00:36:04 +0000 (17:36 -0700)]
systemc: Implement + and - for sc_time, and sc_max_time.
Change-Id: I294b63840e42e2afdef198229adc60ddbb60b9a1
Reviewed-on: https://gem5-review.googlesource.com/12040
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 21 Jul 2018 00:18:22 +0000 (17:18 -0700)]
systemc: Fix a couple memory errors.
Because events are held in vectors, it doesn't make sense to keep an
iterator into the parent to keep track of where that event is for easy
removal since the iterator becomes invalid when the vector is changed.
The events need to be stored in a vector because systemc defines an
accessor which returns that vector, and building a vector on the fly
would be cumbersome.
Also, make sure the Event parent pointer is set to nullptr if there
isn't a parent.
Change-Id: I63a676190e7747e60baaca50009161d47bfc1c54
Reviewed-on: https://gem5-review.googlesource.com/12039
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 20 Jul 2018 23:28:54 +0000 (16:28 -0700)]
systemc: Implement the SC_EXIT_ON_STARVATION exit mode.
This mode implies checking whether there's any activity left either
before starting a delta cycle, or processing delta or timed
notification or timeout.
Change-Id: I0780a1f720cf63f3d2907b8dd28685266b52d6b4
Reviewed-on: https://gem5-review.googlesource.com/12038
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 20 Jul 2018 22:46:49 +0000 (15:46 -0700)]
systemc: Fix the time resolution when constructing an sc_time.
This is (sort of) mandated by the spec. More specifically the spec says
that the systemc API for changing the time resolution can only be
called once, and can only be called before a non-zero sc_time is
constructed.
Because sc_time can be constructed during elaboration and the gem5
version of time resolution is generally not locked down until the
actual simulation starts (after elaboration), the sc_time constructor
needs to call the fixing function itself to ensure that, for instance,
the scaling factors for various real life time units within gem5 are
initialized.
Change-Id: Ied4b43659834761b55b5ae49ea62779af891d9e3
Reviewed-on: https://gem5-review.googlesource.com/12037
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 20 Jul 2018 00:32:34 +0000 (17:32 -0700)]
systemc: Handle event notifications scheduled before sc_start.
After sc_start is called, gem5 has run far enough to have an event
queue to schedule the notification events on. Before then, it's still
legal to request a timed notification. The scheduler should keep track
of those requests, and once an event queue is available it should
add them to it.
Change-Id: Ie7445b1f2e616f4bd36044a09dbef9e1d12d7350
Reviewed-on: https://gem5-review.googlesource.com/12036
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 20 Jul 2018 00:12:31 +0000 (17:12 -0700)]
systemc: Make orphans top level objects instead of panic-ing.
When a simulation ends, the sc_objects it contains are destroyed one
by one, not necessarily in hierarchy order. That means that a parent
object can legitimately be destroyed before its children. Instead of
panic-ing when that inevitably happens, this change makes gem5 turn
those children into top level objects.
Change-Id: Icad9c99310fbc3ddcadbbb4f8a990b4fbfe35bdf
Reviewed-on: https://gem5-review.googlesource.com/12035
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 19 Jul 2018 23:53:27 +0000 (16:53 -0700)]
systemc: Implement some of the basics of sc_time.
This is a very incomplete implementation, but is enough to unblock
implementing some other dependent features.
Change-Id: Ibd2f3476fe01389e277c6956d48337f551d14acd
Reviewed-on: https://gem5-review.googlesource.com/12034
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 19 Jul 2018 22:51:24 +0000 (15:51 -0700)]
systemc: Implement the various sc_module stage callbacks.
This change also gets rid of the SystemC namespace which was
deprecated in favor of sc_gem5.
A few utility functions which check whether certain callbacks have
finished were also implemented. status tracking moved from a global
variable in sc_main.cc to a member of the kernel simobject.
Change-Id: I50967fae9c576fbe45b1faff587aaa824857a289
Reviewed-on: https://gem5-review.googlesource.com/12033
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 11 Sep 2018 07:59:56 +0000 (00:59 -0700)]
base: Avoid dividing by zero in Time::[gs]etTick.
Those functions used the value SimClock::Int::ns which, if the time
resolution is larger than 1ns, can/will be zero. That will make
getTick always return zero, and setTick divide by zero. This change
modifies those functions so that the math they do avoids using any
integer Ticks per time unit value except for Frequency. It seems
unlikely that the Ticks will increment at less than 1Hz.
Change-Id: I5cc9db14699c00dcbff48e4593b98522b13b4ccd
Reviewed-on: https://gem5-review.googlesource.com/12573
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 11 Sep 2018 07:57:34 +0000 (00:57 -0700)]
base: Correct a small typo in sim/core.(hh|cc).
The value GHz with a small z was spelled GHZ with a large z, which was
inconsistent with the other frequency-like values in that namespace.
Change-Id: I55dfc447a5811ae584e46769cd9cadd08bd1e716
Reviewed-on: https://gem5-review.googlesource.com/12572
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 11 Sep 2018 07:55:28 +0000 (00:55 -0700)]
base: Save and restore the width setting of streams used with cprintf.
The flags, precision, and fill character were all being saved and
restored, but cprintf might also change the width setting of the
stream, and that wasn't being saved or restored and could leak from
the cprintf statement.
This change adds the code to save and restore that value.
Change-Id: Ibedb26f7f538cd3be4fe0462d2ee4e5efd62bc59
Reviewed-on: https://gem5-review.googlesource.com/12571
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Pin-Yen Lin [Tue, 14 Aug 2018 06:23:25 +0000 (14:23 +0800)]
net: Fix a bug when receiving fragamented packets
In the previous implementation, the function EtherTap::recvReal will only
read one packet when received some ``interrupt'' (explicitly, when async_IO
set to true). When someone tries to send a large message to the simulated
device, the message will be divided to several packets due to packet
fragmentation. In this situation recvReal will only read one packet and
left the other packets in the buffer. This significantly increases the
networking latency. So before reading from socket, I change the socket into
non-blocking mode and keep reading from it until there's no packet left.
Change-Id: Ieb94a8532cd3994862b6f3eb9474caf7ccf617da
Reviewed-on: https://gem5-review.googlesource.com/12338
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Wed, 29 Aug 2018 10:36:22 +0000 (11:36 +0100)]
base: Fix isSubset() for addr ranges with interleaving
This change extends isSubset() which checks whether the range is a
subset of an input range to support address ranges with interleaving
and hashing.
Change-Id: I3dc9ceccb189b7c8665de0355f0555fc2c37d872
Reviewed-on: https://gem5-review.googlesource.com/12319
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Thu, 30 Aug 2018 09:26:31 +0000 (10:26 +0100)]
configs: Use the same address ranges for dir and mem_ctrls
In Ruby, for every directory we create one memory controller for every
range in the memory ranges. Previously the memory controllers and the
directories created their address ranges independently and as a result
a mismatch was possible. In fact, we assinged an interleaved address
range with hasing for the memory controllers while the corresponding
directories would be assigned the same interleaved address range
without hashing.
This change uses the address range of the memory controllers to
populate the list of address ranges for the corresponding directory
and avoid bugs due to code duplication.
Change-Id: I1e321c81a254199e5aaa9f3b81f4a4642c60a67a
Reviewed-on: https://gem5-review.googlesource.com/12318
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Giacomo Travaglini [Thu, 30 Aug 2018 16:48:48 +0000 (17:48 +0100)]
dev-arm: Make GenericTimer use standard ArmInterruptPin
This patch is deleting the custom ArchTimer::Interrupt implementation in
favour of the standard ArmInterruptPin.
Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12402
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Thu, 30 Aug 2018 15:43:02 +0000 (16:43 +0100)]
dev-arm: Factory SimObject for generating ArmInterruptPin
With this patch the python ArmInterruptPin SimObject matches to the
C++ ArmInterruptPinGen. The latter is in charge of generating
the ArmInterruptPin (which is not a SimObject anymore).
This is meant to ease the generation of ArmInterruptPins: by
not being SimObjects we are not forced to instantiate them
in the configuration script; we can generate them dynamically
instead throughout simulation.
Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12401
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 23 Mar 2017 18:54:56 +0000 (18:54 +0000)]
arm: Use the interrupt adaptor in the PMU
Rewrite interrupt handling in the PMU model to use the new interrupt
adaptor.
Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12400
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Andreas Sandberg [Thu, 23 Mar 2017 18:57:41 +0000 (18:57 +0000)]
arm: Add support for tracking TCs in ISA devices
ISA devices typically need to keep track of the thread context they
are associated with. Among other things, this is required for
interrupt delivery. Add a BaseISADevice:setThreadContext() method to
wire such models to the right thread context.
Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Andreas Sandberg [Thu, 22 Mar 2018 17:58:59 +0000 (17:58 +0000)]
dev, arm: Add misc reg tracing to the generic timer
Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12398
Giacomo Travaglini [Tue, 28 Aug 2018 14:34:34 +0000 (15:34 +0100)]
dev-arm: Create a getter for ArmInterruptPin ID number
A pin owner might want to know which is the irq number
associated with the pin.
Change-Id: I095393d4d25efe13eb2a75a0b0b055d386c2c126
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12298
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Matteo Andreozzi [Fri, 4 Aug 2017 10:11:53 +0000 (11:11 +0100)]
mem: Make DRAMCtrl a QoS-aware Memory Controller
This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no
policy" as a default policy.
Change-Id: I48163da8c8208498cf0398b07094cb840272507f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11973
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Thu, 10 May 2018 16:07:42 +0000 (17:07 +0100)]
mem: Implement base QoS Policies.
This patch implements a base fixed priority policy and an ideal
turnaround policy for the QoS memory controller.
Change-Id: I38ce16f845fc0ec86d6fc4cc5dc5406f213a465e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11972
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Matteo Andreozzi [Thu, 10 May 2018 20:59:08 +0000 (21:59 +0100)]
mem: Add a simple QoS-aware Memory Controller
This patch implements QoSMemorySink: a simple generic QoS-aware memory
controller which inherits from QoS::MemCtrl.
Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11971
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matthew Poremba <porembam@gmail.com>
Matteo Andreozzi [Wed, 10 Jan 2018 13:38:47 +0000 (13:38 +0000)]
mem: Add a QoS-aware Memory Controller type
This is the implementation of QoS algorithms support for gem5 memory
objects. This change-list provides a framework for specifying QoS
algorithm which can be used to prioritise service to specific masters in
the memory controller.
The QoS support implemented here is designed to be extendable so that
new QoS algorithms can be easily plugged into the memory controller as
"QoS Policies".
Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11970
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Thu, 10 May 2018 13:37:27 +0000 (14:37 +0100)]
sim: Add System method for MasterID lookup
A new method (lookupMasterId) has been added to the System. A client
should use it when querying the System for the MasterID of a particular
master. It changes from getMasterId since it is
not registering a new MasterID if the master is not found in the
master's list.
Change-Id: I701158d22e235085bba9ab91154fbb702cae1467
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Daniel R. Carvalho [Fri, 9 Mar 2018 14:47:33 +0000 (15:47 +0100)]
mem-cache: Create Skewed Assoc placement policy
Create a class that implements the skewed associative placement
policy. It uses the hash function and expansions of the skewing
functions described in "Skewed-Associative caches", by Seznec.
Only 8 skewing functions are implemented, and therefore if more
are needed a hash function will be recursively applied on top
of the output of one of these functions to generate different
values. This is not optimal, and if more functions are needed
it might be more effective to implement them.
Change-Id: Ibc77edffd8128114a8b200cec5d8deedfb5105cb
Reviewed-on: https://gem5-review.googlesource.com/8886
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Pin-Yen Lin [Mon, 13 Aug 2018 06:23:24 +0000 (14:23 +0800)]
net: Fix a bug when handling IPv6 packets
When gem5 runs with the networking support, it will run into an assertion
fail and aborted. This is because it tries to calculate checksum for IPv6
packet and this makes the IpPtr pointer ``ip'' become NULL. For that there
is functions and classes for IPv6 in base/inet.cc, I added IPv6 support for
i8254xGBe.cc. Because IPv6 header does not have identification number, I
ignored some of the debug messages using ip->id().
Change-Id: Ida5e36aefd2c5c26053f8152a0aac24191e7757c
Reviewed-on: https://gem5-review.googlesource.com/12339
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 19 Jul 2018 03:59:56 +0000 (20:59 -0700)]
systemc: Implement pending activity related functions
Track the number of notifications/timeouts that are scheduled at any
given time. This lets us implement sc_pending_activity_at_current_time,
sc_pending_activity_at_future_time, and sc_time_to_pending_activity.
Change-Id: Ia3fcd29bdbfe1a6c77eb52ce4836982d4705263c
Reviewed-on: https://gem5-review.googlesource.com/12032
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 17 Jul 2018 07:09:59 +0000 (00:09 -0700)]
systemc: Implement sc_pause, sc_stop, and re-sc_start-ing.
This change further modifies the scheduler to implement the sc_pause
and sc_stop functions, and to ensure that calling sc_start again works.
Also, some small changes were made to how processes and contexts are
hooked up. Now, rather than checking whether a process is running to
determine wether it started on its own or needs to be started manually,
there's a bool which explicitly tracks whether it needs this step. The
problem was that once a thread finished, it wasn't considered running
any more. In that case it had run but finished, but that was
indistinguishable from it needing to run but not having been started.
Change-Id: I3aefb5493f91d9efa1a1382586196339b67925fe
Reviewed-on: https://gem5-review.googlesource.com/12031
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 17 Jul 2018 03:23:21 +0000 (20:23 -0700)]
systemc: Implement sc_get_current_process_handle's other personality.
When run during simulation, sc_get_current_process_handle returns a
handle for the currently running process or a invalid handle if no
process is running (ie sc_main is running).
When run during elaboration, it returns a handle to the most recently
created process. This second context is what this change handles.
Change-Id: I3fb247b9b7bf83891c782966cfef474753159158
Reviewed-on: https://gem5-review.googlesource.com/12030
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 16 Jul 2018 23:44:07 +0000 (16:44 -0700)]
systemc: Handle suspended processes and handle sensitivity overload.
This change keeps track of whether a process would have become ready
but was suspended so that it can become ready when the process is
resumed.
Also, this makes a process ignore its static sensitivity while a
dynamic sensitivity is in place.
Change-Id: If3f6c62f370051e574f81bf227746db8c43527e2
Reviewed-on: https://gem5-review.googlesource.com/11715
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 16 Jul 2018 23:25:32 +0000 (16:25 -0700)]
systemc: Implement next_trigger and wait.
These set up dynamic sensitivity.
Change-Id: I6cf2c2e4f93fe001eb7df8377753d51846b57d32
Reviewed-on: https://gem5-review.googlesource.com/11714
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 16 Jul 2018 23:14:33 +0000 (16:14 -0700)]
systemc: Implement the sensitivity mechanism.
This change lets processes be sensitive to events, timeouts, etc.
Change-Id: If30a256dfa8a2e92192c1f9c96b48e2aa28ec27e
Reviewed-on: https://gem5-review.googlesource.com/11713
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 16 Jul 2018 22:53:04 +0000 (15:53 -0700)]
systemc: Hook up sc_time_stamp sc_delta_count.
sc_time_stamp reports the current simulation time. sc_delta_count was
hooked up to a dummy value. This change hooks it up to the scheduler so
that it returns the real value.
Change-Id: I354c4be32161eabeea86af653f5cb0a5d384645b
Reviewed-on: https://gem5-review.googlesource.com/11712
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 12 Jul 2018 03:00:50 +0000 (20:00 -0700)]
systemc: Implement much of events, event lists and event exprs.
Three things aren't yet implemented, waking up processes which are
sensitive to the event, triggering of events, and garbage collecting
list objects which came from expression objects.
The garbage collection aspect is problematic since there doesn't seem
to be a correct way to implement it given the constraints in the spec,
including the way that's implemented by Accellera. It's something that
will need to be dealt with at some point, but in the interest of
forward progress it's being ignored for now.
Change-Id: Ic4e3c219ff482729f1f1302ab10181a798d48041
Reviewed-on: https://gem5-review.googlesource.com/11711
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 5 Jul 2018 05:41:29 +0000 (22:41 -0700)]
systemc: Implement channel updates and rework the scheduler.
This change implements channel updates, and also reworks the scheduler
to delegate more to the gem5 event queue by taking advantage of
event priorities to ensure things happen in the right order. There's
a lengthy comment in scheduler.hh describes how that all works.
Change-Id: I5dee71b86b2e612bb720a4429f3a72e4b7c6d01f
Reviewed-on: https://gem5-review.googlesource.com/11710
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 3 Jul 2018 23:41:30 +0000 (16:41 -0700)]
systemc: Partially implement the scheduler.
This change implements the "evaluate" part of the delta cycles, and
sketches out a function to run delta cycles and the initialization
phase. The kernel object now schedules an event at time zero which
runs the initialization phase.
Also, some small places which were stubbed out pending a way to check
the currently running process have been filled in now that that's
being tracked.
Change-Id: I6899569eb0195ff1c059fa4e68e90ef162b2f2df
Reviewed-on: https://gem5-review.googlesource.com/11709
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 29 Jun 2018 23:46:52 +0000 (16:46 -0700)]
systemc: Fill out sc_process_handle and create Process classes.
The sc_process_handle class now primarily delegates to a Process object
it points at. The Process object does book keeping as far as its
internal state, but doesn't yet have a way to run its target function
or to schedule itself or inject exceptions into its context of
execution.
Change-Id: I98389778abe29aa26e3e3a91bf02e6721acc8a9c
Reviewed-on: https://gem5-review.googlesource.com/11613
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 26 Jun 2018 03:37:58 +0000 (20:37 -0700)]
systemc: Implement some basic plumbing in sc_module.hh.
Take care of some low hanging fruit as far as wrapper methods and
the sc_bind_proxy class.
Change-Id: I7f55a37eeaa82338bd608218c0261fbc39e65fc2
Reviewed-on: https://gem5-review.googlesource.com/11612
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Jun 2018 21:19:44 +0000 (14:19 -0700)]
systemc: Implement most of sc_object.
To avoid making it hard to change sc_object's implementation in the
future, this change keeps most of the data members out of sc_object and
keeps them in a seperate Object which is managed independently but
still matches to the sc_objects one to one.
This change also moves away from the SystemC/sc_gem5 namespace pair in
favor of sc_gem5. Having two namespaces with classes, etc, living in
both was complicating things. Having to use a namespace that doesn't
fit in one scheme or the other isn't great, but it's the lesser of two
evils.
Change-Id: Ib59c3c515ca98c7fe519c59e9fe9270304b71cc0
Reviewed-on: https://gem5-review.googlesource.com/11611
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Jun 2018 21:15:28 +0000 (14:15 -0700)]
systemc: Get sc_main to work even when dynamically linked.
Unfortunately multiply defined weak symbols don't work like they're
supposed to when the different versions are across dynamic linking
boundaries.
Fortunately, a weak symbol with no definition at all will still
consistently evaluate as 0, and a singularly defined weak symbol will
still resolve correctly.
Instead of relying on a weak version of sc_main being overridden by a
strong/non-default definition, this change leaves it as undefined and
detects at run time whether the symbol resolves to 0 or to an actual
code location.
Change-Id: I31c4ff769b0c52277c6cf4845ca3f85000009583
Reviewed-on: https://gem5-review.googlesource.com/11610
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Jun 2018 21:14:47 +0000 (14:14 -0700)]
systemc: Implement the sc_attr classes.
Change-Id: Ibbe6da957b1b36687178f226e80718adc0f4ab81
Reviewed-on: https://gem5-review.googlesource.com/11609
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 02:30:23 +0000 (19:30 -0700)]
systemc: Disable tests which use sensitive_(pos|neg).
Those members are deprecated and not worth supporting.
Change-Id: I30b64b36ba3201bb0bcbb541da512676c2bf8510
Reviewed-on: https://gem5-review.googlesource.com/11357
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 02:09:56 +0000 (19:09 -0700)]
systemc: Enable some more sc_simcontext related tests.
Now that we bit the bullet and stubbed out sc_simcontext and related
functions a little bit, we can enable a couple more tests. This change
also adds in some functions the new tests expect sc_simcontext to have.
Change-Id: I00b5cc0c6eb658eb689b9c85ed171f290009768d
Reviewed-on: https://gem5-review.googlesource.com/11356
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 02:07:14 +0000 (19:07 -0700)]
systemc: Add m_cur_val and m_new_val to sc_signal.
These members are referred to in one of the tests.
Change-Id: Iab0110a0e3acf627986664069622704f17b703a1
Reviewed-on: https://gem5-review.googlesource.com/11355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 01:51:21 +0000 (18:51 -0700)]
systemc: Add the "implementation defined" vport function.
This function is in an "implementation defined" class body in the spec,
and has a comment next to it which says "(for internal use only)" next
to it, but it is still used directly in one of the tests.
Change-Id: Ib3727c93cc531ddd31a24897291dc7e7c97c2b58
Reviewed-on: https://gem5-review.googlesource.com/11354
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 00:50:08 +0000 (17:50 -0700)]
systemc: Add the nonstandard sc_join class and sc_thread_handle type.
Change-Id: I09905bad4797d9c456229afe601006ce16977394
Reviewed-on: https://gem5-review.googlesource.com/11353
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Sean Wilson [Fri, 17 Aug 2018 22:48:34 +0000 (17:48 -0500)]
testlib: No catch of custom exceptions in sandbox
Custom exceptions are not always properly pickled which could lead to
the sandbox test executor to crash when it tries to re __init__ pickled
exceptions thrown from the failed test.
Change-Id: I4e2ffe5802dda668b5d61c5a16e0989717121a04
Signed-off-by: Sean Wilson <spwilson27@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/12167
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Andreas Sandberg [Tue, 28 Aug 2018 10:56:55 +0000 (11:56 +0100)]
config: Move KVM CPU checking to CpuConfig helper module
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is
somewhat involved since CPUs can be disabled at compile time. Enable
better code reuse by moving it to the CpuConfig module.
Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12418
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Tue, 19 Jun 2018 00:17:35 +0000 (17:17 -0700)]
systemc: Minimally implemented the deprecated sc_simcontext.
This is supposed to be deprecated, but is still used in a small way
by the tests.
Change-Id: I94fc32f9e0f03d50c00ce5421926203859064020
Reviewed-on: https://gem5-review.googlesource.com/11352
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 19 Jun 2018 00:04:28 +0000 (17:04 -0700)]
systemc: Add a minimal version of the deprecated sc_process_b.
This type is deprecated, but some tests still rely on it. This change
adds just enough of it to satisfy the tests, and also the several
different mechanisms for retrieving the sc_process_b which refers to
the currently active process.
Change-Id: Id122ae5df23744b5de1e1c97573412f97a73b77a
Reviewed-on: https://gem5-review.googlesource.com/11351
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 18 Jun 2018 22:14:24 +0000 (15:14 -0700)]
systemc: Add bind() to sc_port_base.
sc_port_base is supposed to be implementation defined, but internal
details of it are relied on by the systemc tests.
Change-Id: I53d84e708a5543a2cf4bd0deffc2efea1c008d97
Reviewed-on: https://gem5-review.googlesource.com/11350
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 17 Jun 2018 05:42:22 +0000 (22:42 -0700)]
systemc: Make the verify.py --list option print a total count.
Make the --list option of verify.py print a count of how many tests it
printed. Because --list respects the filter options, this is an easy
way to check how many tests have certain properties.
Change-Id: I03fac349a946631c20c8e6b49e0ad8934872898e
Reviewed-on: https://gem5-review.googlesource.com/11288
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>