dev, arm: Add misc reg tracing to the generic timer

Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12398

diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 1d5e8bb00fab76365535813c62d3f7ff0debb986..260461e337b2b052d89c2088920e3f5c9920efdf 100644 (file)
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015, 2017 ARM Limited
+ * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -521,6 +521,20 @@ GenericTimer::readMiscReg(int reg, unsigned cpu)
 }
 
 
+void
+GenericTimerISA::setMiscReg(int reg, MiscReg val)
+{
+    DPRINTF(Timer, "Setting %s := 0x%x\n", miscRegName[reg], val);
+    parent.setMiscReg(reg, cpu, val);
+}
+
+MiscReg
+GenericTimerISA::readMiscReg(int reg)
+{
+    MiscReg value = parent.readMiscReg(reg, cpu);
+    DPRINTF(Timer, "Reading %s as 0x%x\n", miscRegName[reg], value);
+    return value;
+}
 
 GenericTimerMem::GenericTimerMem(GenericTimerMemParams *p)
     : PioDevice(p),

diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 2c5776590dde66e6409372a7cda0336fb534e5c7..1c9449e058af6c0e8bdc6f3318acca11638fce5a 100644 (file)
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, 2015, 2017 ARM Limited
+ * Copyright (c) 2013, 2015, 2017-2018 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -318,12 +318,8 @@ class GenericTimerISA : public ArmISA::BaseISADevice
     GenericTimerISA(GenericTimer &_parent, unsigned _cpu)
         : parent(_parent), cpu(_cpu) {}
 
-    void setMiscReg(int misc_reg, ArmISA::MiscReg val) override {
-        parent.setMiscReg(misc_reg, cpu, val);
-    }
-    ArmISA::MiscReg readMiscReg(int misc_reg) override {
-        return parent.readMiscReg(misc_reg, cpu);
-    }
+    void setMiscReg(int misc_reg, ArmISA::MiscReg val) override;
+    ArmISA::MiscReg readMiscReg(int misc_reg) override;
 
   protected:
     GenericTimer &parent;