egl/dri2: Log a warning if no platforms are enabled.

If you hit this, you didn't compile with --with-egl-platforms=...

Recompile with something like --with-egl-platforms=x11,drm and make
clean and make again.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Drop BRW_NEW_VERTEX_PROGRAM and _NEW_TRANSFORM from Gen4 VS state.

These stopped being necessary in commit ab973403e445cd8211dba4e87e0.

v2: Update commit message with a better explanation (thanks to Eric
    Anholt for doing the git archaeology).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Drop BRW_NEW_VERTEX_PROGRAM from Gen7+ 3DSTATE_VS atoms.

We don't access brw->vertex_program or ctx->_Shader since the previous
commit, so we don't need this dirty bit.

I think it's still necessary on Gen6 because it still conflates
constant uploading with unit state uploading.  We can fix that later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Store floating point mode choice in brw_stage_prog_data.

We use IEEE mode for GLSL programs, but need to use ALT mode for ARB
programs so that 0^0 == 1.  The choice is based entirely on the shader
source language.

Previously, our code to determine which mode we wanted was duplicated
in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8).
The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing
as well - we use CurrentProgram (non-derived state), but _Shader
(derived state).  It also relies on knowing that ARB programs don't
use gl_shader_program structures today.  The compiler already makes
this assumption in a few places, but I'd rather keep that assumption
out of the state upload code.

With this patch, we select the mode at compile time, and store that
choice in prog_data.  The state upload code simply uses that decision.

This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too.

Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than
ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code.

This might fix SSO related bugs, but ALT mode is only used for ARB
programs, so if there's an actual problem, it's likely no one would
run into it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move PSCDEPTH calculations from draw time to compile time.

The "Pixel Shader Computed Depth Mode" value is entirely based on the
shader program, so we can easily do it at compile time.  This avoids the
if+switch on every 3DSTATE_WM (Gen7)/3DSTATE_PS_EXTRA (Gen8+) upload,
and shares a bit more code.

This also simplifies the PMA stall code, making it match the formula
more closely, and drops a BRW_NEW_FRAGMENT_PROGRAM dependency.  (Note
that the previous comment was wrong - the code and the documentation
have != PSCDEPTH_OFF, not ==.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

freedreno/a4xx: unify vertex/texture formats into a single table

Similar to the scheme that Ilia put in place for a3xx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: fd4_util -> fd4_format

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers / a4xx fmt rename

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965: Add var->location != -1 assertions.

We shouldn't receive variables with invalid locations set - adding these
assertions should help catch problems before they cause crashes later.

Inspired by similar code in st_glsl_to_tgsi.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Don't offset uniform registers in half().

Half gives you the second half of a SIMD16 register, but if the register
is a uniform it would incorrectly give you the next register.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

freedreno/a4xx: frag-depth fixes

Also seems to fix kill/discard.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

linker: Assign varying locations geometry shader inputs for SSO

Previously only geometry shader outputs would be assigned locations if
the geometry shader was the only stage in the linked program.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

linker: Wrap access of producer_var with a NULL check

producer_var could be NULL if consumer_var is not NULL and
consumer_is_fs is false.  This will occur when the producer is NULL and
the consumer is the geometry shader for a program that contains only a
geometry shader.  This will occur starting with the next patch.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

st/xvmc: Fix compiler warnings

Mostly signed/unsigned comparison

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/nine: Fix vertex declarations for non-standard (usage/index)

Nine code to match vertex declaration to vs inputs was limiting
the number of possible combinations.

Some sm3 games have issues with that, because arbitrary (usage/index)
can be used.

This patch does the following changes to fix the problem:
. Change the numbers given to (usage/index) combinations to uint16
. Do not put limits on the indices when it doesn't make sense
. change the conversion rule (usage/index) -> number to fit all combinations
. Instead of having a table usage_map mapping a (usage/index) number to
an input index, usage_map maps input indices to their (usage/index)

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: sm1_declusage_to_tgsi, do not restrict indices with TGSI_SEMANTIC_GENERIC

With sm3, you can declare an input/output with an usage and an usage index.

Nine code hardcodes the translation usage/index to a corresponding TGSI code.
The translation was limited to a few usage/index combinations that were corresponding
to most of the needs of games, but some games did not work.

This patch rewrites that Nine code to map all possible usage/index combination
to TGSI code. The index associated to TGSI_SEMANTIC_GENERIC doesn't need to be low
for good performance, as the old code was supposing, and is not particularly bounded
(it's UINT16). Given the index is BYTE, we can map all combinations.

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: Always return D3D_OK when issuing with D3DISSUE_BEGIN

This is the behaviour that Wine tests.

Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: always succeed for D3DQUERYTYPE_TIMESTAMP when flushing

This is the behaviour that Wine tests

Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: allow app to call GetData without Issuing first

Nine was allowing that behaviour, but was not filling the result.

Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: Fix D3DISSUE_END behaviour.

Issuing D3DISSUE_END should:
. reset previous queries if possible
. end the query

Previous behaviour wasn't calling end_query for
queries not needing D3DISSUE_BEGIN, nor resetting
previous queries.

This fixes several applications not launching properly.

Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: return S_FALSE instead of INVALIDCALL when in building query state

It is the same behaviour as wine has.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: Use gallium caps to get if queries are supported. (v2)

Some queries need the driver to advertise a cap to be supported.
For example r300 doesn't support them.

v2 (David): check also for PIPE_CAP_QUERY_PIPELINE_STATISTICS, fix wine
            tests on r300g

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: Remove flush logic

get_query_result flushes automatically, we don't need to flush.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

st/nine: Queries: remove dummy queries

Applications are supposed to call CreateQuery with a NULL
ppQuery to know if the query is supported. We supported that.

However when ppQuery was not NULL, we were accepting to create the
query and were creating a dummy query even when the query is not
supported.

Wine has different behaviour. This patch drops the dummy queries
support and matches wine behaviour.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

freedreno/a3xx: implement anisotropic filtering

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: rect textures

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: fix signed vs unsigned lols

Signed-off-by: Rob Clark <robclark@freedesktop.org>

gallivm: Update for RTDyldMemoryManager becoming an unique_ptr.

Trivial.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=86958

glsl: throw error when using invariant(all) in a fragment shader

Note that some of the GLSL specifications explicitly state this as
compile error, some simply state that 'it is an error'.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/skl: Fix SBE state upload code.

The state upload code was incorrectly shifting the attribute swizzles. The
effect of this is we're likely to get the default swizzle values, which disables
the component.

This doesn't technically fix any bugs since Skylake support is still disabled by
default (no PCI IDs).

While here, since VARYING_SLOT_MAX can be greater than the number of attributes
we have available, add a warning to the code to make sure we never do the wrong
thing (and hopefully prevent further static analysis from finding this).
Admittedly I am a bit confused. It seems to me like the moment a user has
greater than 8 varyings we will hit this condition. CC Ken to clarify.

v2: Forgot to git add the warning message in v1

v3: Change the > 31 varyings to an assertion (Ken)

Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> (via Coverity)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600, llvm: Don't leak global symbol offsets

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

i965: Avoid union literal, for old gcc compatibility.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Remove tabs from instruction scheduler.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/vs: Set brw_vs_prog_key::clamp_vertex_color to 0 when irrelevant.

Vertex color clamping is only relevant if the shader writes to
the built-in gl_[Secondary]{Front,Back}Color varyings.  Otherwise,
brw_vs_prog_key::clamp_vertex_color is never used, so we can simply
leave it set to 0.

This enables us to correctly predict the clamp_vertex_color key value
in the precompile for shaders which don't use those varyings.

Eliminates virtually all VS recompiles in Serious Sam 3's intro.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Make vertex color clamp handling code VS specific.

Vertex color clamping only applies to gl_[Secondary]{Front,Back}Color,
which are compatibility-only built-in varyings.  We only support GS in
core profile, so they can't exist in geometry shaders.

We can drop several dirty bits from the GS program key - they're
unnecessary for a core profile implementation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/vs: Handle vertex color clamping in emit_urb_slot().

Vertex color clamping only applies to a few specific built-ins: COL0/1
and BFC0/1 (aka gl_[Secondary]{Front,Back}Color).  It seems weird to
handle special cases in a function called emit_generic_urb_slot().

emit_urb_slot() is all about handling special cases, so it makes more
sense to handle this there.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Use the enum type for gen6_gather_wa sampler key field.

Requested by Matt Turner.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Drop use of GL types in program keys.

This is really far removed from the API; we should just use C types.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Move program key structures to brw_program.h.

With fs_visitor/fs_generator being reused for SIMD8 VS/GS programs,
we're running into weird #include patterns, where scalar code #includes
brw_vec4.h and such.

Program keys aren't really related to SIMD4X2/SIMD8 execution - they
mostly capture NOS for a particular shader stage.  Consolidating them
all in one place that's vec4/scalar neutral should help avoid problems.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Delete brw_state_flags::cache and related code.

It's been merged into brw_state_flags::brw for simplicity and
efficiency.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).

I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.

I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.

Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.

v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
    state-based recompiles, and nix the "proper subset" claim,
    as it's false. (Caught by Kristian Høgsberg).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.

Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache.  Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.

State upload is one of the hottest paths in the driver.  For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache).  Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom.  Broadwell, for example, has
57 state atoms, so this small savings can add up.

CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset).  Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.

Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones.  This one simply renames things, and was made via:

$ for file in *.[ch]; do
      sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
             -e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
  done

Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw.  It will also fix the
alphabetization issues.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>

i965: Remove "disable_derivative_optimization" driconf option.

This was added in September 2013 when we first implemented the fast
(but lower quality) derivatives.  A quick Google search didn't turn
up anyone using or recommending the option, so I suspect no one does.

Applications that want to control the quality of their derivatives can
use the new GL_ARB_derivative_control extension, or use the glHint
mechanism.  The driconf option seems superfluous.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Just return void from brw_try_draw_prims

Note from Ken:

    "We used to use the return value to indicate whether software
    fallbacks were necessary, but we haven't in years."

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Use current Mesa coding style in check_valid_to_render

This makes some others patches (still in my local tree) a bit cleaner.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Use unreachable instead of assert in check_valid_to_render

This is generally the prefered style these days.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Silence unused parameter warnings in _mesa_validate_Draw functions

../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawElements':
../../src/mesa/main/api_validate.c:376:37: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_MultiDrawElements':
../../src/mesa/main/api_validate.c:394:65: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawRangeElements':
../../src/mesa/main/api_validate.c:452:35: warning: unused parameter 'basevertex' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawArrays':
../../src/mesa/main/api_validate.c:473:25: warning: unused parameter 'start' [-Wunused-parameter]
../../src/mesa/main/api_validate.c: In function '_mesa_validate_DrawElementsInstanced':
../../src/mesa/main/api_validate.c:590:44: warning: unused parameter 'basevertex' [-Wunused-parameter]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Refactor common validation code to validate_DrawElements_common

Most of the code in _mesa_validate_DrawElements,
_mesa_validate_DrawRangeElements, and
_mesa_validate_DrawElementsInstanced was the same.  Refactor this out to
common code.

As a side-effect, a bug in _mesa_validate_DrawElementsInstanced was
fixed.  Previously this function would not generate an error when
check_valid_to_render failed if numInstances was 0.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Generate GL_INVALID_OPERATION when drawing w/o a VAO in core profile

GL 3-ish versions of the spec are less clear that an error should be
generated here, so Ken (and I during review) just missed it in 1afe335.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: fix height error check for 1D array textures

height=0 is legal for 1D array textures (as depth=0 is legal for
2D arrays).  Fixes new piglit ext_texture_array-errors test.

Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>

r600, llvm: Fix mem leak

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

clover: clCompileProgram CL_INVALID_COMPILER_OPTIONS

clCompileProgram should return CL_INVALID_COMPILER_OPTIONS
instead of CL_INVALID_BUILD_OPTIONS

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

vc4: Pair up QPU instructions when scheduling.

We've got two mostly-independent operations in each QPU instruction, so
try to pack two operations together.  This is fairly naive (doesn't track
read and write separately in instructions, doesn't convert ADD-based MOVs
into MUL-based movs, doesn't reorder across uniform loads), but does show
a decent improvement on shader-db-2.

total instructions in shared programs: 59583 -> 57651 (-3.24%)
instructions in affected programs:     47361 -> 45429 (-4.08%)

r600g/sb: fix issues cause by GLSL switching to loops for switch

Since 73dd50acf6d244979c2a657906aa56d3ac60d550
glsl: implement switch flow control using a loop

The SB backend was falling over in an assert or crashing.

Tracked this down to the loops having no repeats, but requiring
a working break, initial code just called the loop handler for
all non-if statements, but this caused a regression in
tests/shaders/dead-code-break-interaction.shader_test.
So I had to add further code to detect if all the departure
nodes are empty and avoid generating an empty loop for that case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86089
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-By: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

freedreno/a4xx: alpha blend fixes

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: fix DRAW initiator encoding of index size

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965/vec4: Rewrite dead code elimination to use live in/out.

Improves 359 shaders by >=10%
         114 shaders by >=20%
          91 shaders by >=30%
          82 shaders by >=40%
          22 shaders by >=50%
           4 shaders by >=60%
           2 shaders by >=80%

total instructions in shared programs: 5845346 -> 5822422 (-0.39%)
instructions in affected programs:     364979 -> 342055 (-6.28%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Track liveness of the flag register.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Remove opt_drop_redundant_mov_to_flags().

Dead code elimination now handles this.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use const fs_reg & rather than a copy or pointer.

Also while we're touching var_from_reg, just make it an inline function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Dead code eliminate instructions writing the flag.

Most prominently helps Natural Selection 2, which has a surprising
number shaders that do very complicated things before drawing black.

instructions in affected programs:     21052 -> 16978 (-19.35%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Track liveness of the flag register.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use local pointer to block_data in live intervals.

The next patch will be simplified because of this, and makes reading the
code a lot easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Make live_intervals part of the vec4_visitor class.

Like in fs_visitor.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Treat the FB_WRITE as predicated if we're discarding.

Pre-Haswell hardware couldn't actually predicate it, but it's easier to
pretend as if it's predicated in the visitor since it will generate a
MOV from f0.1.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't treat IF or WHILE with cmod as writing the flag.

Sandybridge's IF and WHILE instructions can do an embedded comparison
with conditional mod.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: Disassemble tdr and tm registers properly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

main, glsl: Bump max known desktop glsl version to 4.50

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl/cs: Change gl_WorkGroupSize from ivec3 to uvec3

As documented in:

https://www.opengl.org/registry/specs/ARB/compute_shader.txt

  const uvec3 gl_WorkGroupSize;

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: avoid anonymous struct in float <-> VF conversions

Anonymous structures are only supported with newer versions of
GCC.  They will not work with GCC 4.2.1 used by OpenBSD or
GCC 4.4.7 shipped with RHEL6 going by a commit to fix a similiar
problem in radeonsi earlier in the year
(74388dd24bc7fdb9e62ec18096163f5426e03fbf).

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>

mesa: fix arithmetic error in _mesa_compute_compressed_pixelstore()

We need parenthesis around the expression which computes the number of
blocks per row.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>

vbo: also print buffer object pointer in vbo_print_vertex_list()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: some improvements for print_list()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: inline/remove _mesa_polygon_stipple()

Was not called from any other place.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

svga: fix comment typo

mesa: remove unused functions in prog_execute.c

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: update glext.h to version 20141118

gallium: add include path to fix building of pipe-loader code

The pipe-loader code wasn't finding util/u_atomic.h

Reviewed-by: Matt Turner <mattst88@gmail.com>

graw: Avoid 'near'/'far' variables.

They are defined by windows.h, which got included slightly more
frequently than before with u_atomic.h

i965/fs: Clean up some whitespace in reg_allocate.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

ra: Don't use regs as the ralloc context.

The i965 backends pass something out of 'screen', which is allocated
per-process, making using this as a ralloc context not thread-safe.

All callers ra_alloc_interference_graph() already ralloc_free() its
return value.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Initialize INTEL_DEBUG once per process.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965: Initialize compaction tables once per process.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

glsl: Initialize static temporaries_allocate_names once per process.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

util/u_atomic: Fix the unlocked implementation.

It was totally broken:

- p_atomic_dec_zero() was returning the negation of the expected value

- p_atomic_inc_return()/p_atomic_dec_return() was
  post-incrementing/decrementing, hence returning the old value instead
  of the new

- p_atomic_cmpxchg() was returning the new value on success, instead of
  the old

It is clear this never used in the past. I wonder if it wouldn't be better to
yank it altogether.

Reviewed-by: Matt Turner <mattst88@gmail.com>

util/u_atomic: Add a simple test.

It was much easier for me to verify things build and run as expected
with this simple test, than building and testing whole Mesa.

With scons the test can be build and run merely by doing:

  scons u_atomic_test

Building the test with autotools is left as a future exercise.

Reviewed-by: Matt Turner <mattst88@gmail.com>

util: Make u_atomic.h typeless.

like how C11's stdatomic.h provides generic functions. GCC's __sync_*
builtins already take a variety of types, so that's simple.

MSVC and Sun Studio don't, but we can implement it with something that
looks a little crazy but is actually quite readable.

Thanks to Jose for some MSVC fixes!

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: Use stdbool.h's bool rather than "boolean".

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: Remove u_atomic.h's GCC inline assembly.

GCC >= 4.1 support the __sync_* intrinsics. That seems like a
sufficiently old baseline.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: Remove u_atomic.h's MSVC inline assembly.

There was already an intrinsics path that implemented all of the same
functions, plus more.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: Remove u_atomic.h's Gallium dependence.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: s/INLINE/inline/ in u_atomic.h.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: Move u_atomic.h to src/util.

To be shared outside of Gallium.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

vc4: Introduce scheduling of QPU instructions.

This doesn't reschedule much currently, just tries to fit things into the
regfile A/B write-versus-read slots (the cause of the improvements in
shader-db), and hide texture fetch latency by scheduling setup early and
results collection late (haven't performance tested it).  This
infrastructure will be important for doing instruction pairing, though.

shader-db2 results:
total instructions in shared programs: 61874 -> 59583 (-3.70%)
instructions in affected programs:     50677 -> 48386 (-4.52%)

vc4: Drop the explicit scoreboard wait.

This is actually implicitly handled by the TLB operations.

vc4: Also deal with VPM reads at thread end.

Prevents a regression with QPU scheduling, which happens to put the no-op
reads for unused VPM contents end up at the end of the program.

vc4: Fix assertion about SFU versus texturing.

We're supposed to be checking that nothing else writes r4, which is done
by the TMU result collection signal, not the coordinate setup.

Avoids a regression when QPU instruction scheduling is introduced.