Ilia Mirkin [Sun, 15 Jan 2017 18:19:04 +0000 (13:19 -0500)]
nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwell
This had been updated in one place but not the other.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Mon, 16 Jan 2017 20:48:23 +0000 (06:48 +1000)]
radv/ac: use ctx->voidt in more places. (v2)
Just noticed this while in the area.
v2: one replacement was incorrect.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 16 Jan 2017 20:37:36 +0000 (06:37 +1000)]
radv/meta: consolidate the depth stencil clear renderpasses
We only need one per samples (maybe not even that), reduce
all the unneeded ones.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Mon, 16 Jan 2017 19:25:15 +0000 (14:25 -0500)]
nv50/ir: handle new DDIV op which will be used for double divisions
The existing lowering is in place to lower that to RCP + MUL, or fancier
things down the line if necessary.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Nicolai Hähnle [Mon, 16 Jan 2017 15:40:41 +0000 (16:40 +0100)]
tgsi: add DDIV instruction
Double-precision division, to allow more precision than a DRCP + DMUL
sequence.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Mon, 16 Jan 2017 15:44:08 +0000 (16:44 +0100)]
radeonsi: fix R600_DEBUG=nooptvariant
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Kenneth Graunke [Sun, 15 Jan 2017 00:23:10 +0000 (16:23 -0800)]
i965: Make BLORP disable the NP Z PMA stall fix.
This may fix GPU hangs on Gen8. I don't know if it does though.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sat, 14 Jan 2017 06:53:34 +0000 (22:53 -0800)]
i965: Enable OpenGL 4.5 on Haswell.
Everything is in place and the test results look solid.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Marek Olšák [Fri, 6 Jan 2017 00:16:44 +0000 (01:16 +0100)]
radeonsi: implement GL_FIXED vertex format
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Jan 2017 23:30:12 +0000 (00:30 +0100)]
radeonsi: implement 32-bit SNORM/UNORM/SSCALED/USCALED vertex formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Jan 2017 23:07:21 +0000 (00:07 +0100)]
radeonsi: make fix_fetch 64-bit
v2: add u_bit_consecutive64
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Thomas Hindoe Paaboel Andersen [Sat, 14 Jan 2017 23:28:54 +0000 (00:28 +0100)]
gallium/hud: avoid buffer overrun
Renaming data sources was added in
e8bb97ce30051b999a4a69c9b27884daeb8d71e6
It was possible to use a new name longer than
the name array in hud_graph of 128. This
patch truncates the name to fit the array.
CC: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sun, 15 Jan 2017 22:59:00 +0000 (23:59 +0100)]
gallium/radeon: add GPU-shaders-busy HUD query
It should be close to the GPU load, but it can be much lower if something
is stalling shader execution (e.g. CP DMA).
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 15 Jan 2017 22:51:29 +0000 (23:51 +0100)]
gallium/radeon: make the GPU load / GRBM_STATUS monitoring extensible
The next patch will add SPI_BUSY monitoring.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 15 Jan 2017 20:50:54 +0000 (21:50 +0100)]
radeonsi: show average results per frame for perf counters in HUD
so that the graphs are independent from FPS.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 15 Jan 2017 21:28:15 +0000 (22:28 +0100)]
gallium/hud: disable queries during HUD draw calls
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 15 Jan 2017 21:01:39 +0000 (22:01 +0100)]
gallium/hud: increase the vertex buffer size for background quads
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nayan Deshmukh [Fri, 13 Jan 2017 13:15:31 +0000 (18:45 +0530)]
st/va: delay calling begin_frame until we have all parameters
If begin_frame is called before setting intra_matrix and
non_intra_matrix it leads to segmentation faults when
vl_mpeg12_decoder.c is used.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92634
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Kenneth Graunke [Sun, 15 Jan 2017 08:58:20 +0000 (00:58 -0800)]
i965: Use align1 mode for barrier messages.
In commit
7428e6f86ab5 we switched the barrier SEND message's
destination type to UW to avoid problems in SIMD16 compute shaders.
Tessellation control shaders also use barriers, and in vec4 mode, we
were emitting them in align16 mode. The simulator warns that only UD,
D, F, and DF are valid destination types - UW is technically illegal.
So, switch to align1 mode. Either mode should work fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ilia Mirkin [Sun, 15 Jan 2017 17:15:06 +0000 (12:15 -0500)]
nvc0/ir: emit FMZ flag when requested on FFMA
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Connor Abbott [Sat, 14 Jan 2017 23:08:11 +0000 (18:08 -0500)]
nir/gcm: fix a bug with metadata handling
We were using impl->num_blocks, but that isn't guaranteed to be
up-to-date until after the block_index metadata is required. If we were
unlucky, this could lead to overwriting memory.
Noticed by inspection.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 12 Jan 2017 18:56:24 +0000 (18:56 +0000)]
radv: generate entrypoints from vk.xml
v2: rework entry point iteration (Jason)
cleanup unused imports
v3: don't drop header installation (Emil)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Lionel Landwerlin [Thu, 12 Jan 2017 17:02:04 +0000 (17:02 +0000)]
anv: generate entry points from vk.xml
v2: rework entry point iteration (Jason)
cleanup unused imports
v3: don't drop header installation (Emil)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 12 Jan 2017 17:01:44 +0000 (17:01 +0000)]
vulkan: add API registry
Signed-off: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Thu, 12 Jan 2017 15:57:14 +0000 (15:57 +0000)]
include: update Vulkan headers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Andres Rodriguez [Fri, 13 Jan 2017 23:44:17 +0000 (18:44 -0500)]
radv: make device extension setup dynamic
Each physical device may have different extensions than one another.
Furthermore, depending on the software stack, some extensions may not be
accessible.
If an extension is conditional, it can be registered only when
necessary.
v2: removed unused function and fixed indentation
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Andres Rodriguez [Fri, 13 Jan 2017 23:44:16 +0000 (18:44 -0500)]
radv: rename global extension properties structs
All extension arrays are global, but only one of them refers to instance
extensions.
The device extension array refers to extensions that are common across
all physical devices. This disctinction will be more imporant once we
have dynamic extension support for devices.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Andres Rodriguez [Fri, 13 Jan 2017 23:44:15 +0000 (18:44 -0500)]
radv: use a winsys context per-queue, instead of per device v2
Queues are independent execution streams. The vulkan spec provides no
ordering guarantees for different queues.
By using a single context for all queues, we are forcing all commands
into an unecessary FIFO ordering.
This change is a preparation step to allow our-of-ordering scheduling of
certain work tasks.
v2: Fix a rebase error with radv_QueueSubmit() and trace_bo
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Thu, 12 Jan 2017 10:51:56 +0000 (21:51 +1100)]
nir: optimise min/max fadd combos
shader-db results BDW:
total instructions in shared programs:
13060410 ->
13060313 (-0.00%)
instructions in affected programs: 24533 -> 24436 (-0.40%)
helped: 88
HURT: 0
total cycles in shared programs:
256585692 ->
256586698 (0.00%)
cycles in affected programs: 647290 -> 648296 (0.16%)
helped: 35
HURT: 30
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 13 Jan 2017 22:29:52 +0000 (14:29 -0800)]
i965: Move Gen4-5 interpolation stuff to brw_wm_prog_data.
This fixes glxgears rendering, which had surprisingly been broken since
late October! Specifically, commit
91d61fbf7cb61a44adcaae51ee08ad0dd6b.
glxgears uses glShadeModel(GL_FLAT) when drawing the main portion of the
gears, then uses glShadeModel(GL_SMOOTH) for drawing the Gouraud-shaded
inner portion of the gears. This results in the same fragment program
having two different state-dependent interpolation maps: one where
gl_Color is flat, and another where it's smooth.
The problem is that there's only one gen4_fragment_program, so it can't
store both. Each FS compile would trash the last one. But, the FS
compiles are cached, so the first one would store FLAT, and the second
would see a matching program in the cache and never bother to compile
one with SMOOTH. (Clearing the program cache on every draw made it
render correctly.)
Instead, move it to brw_wm_prog_data, where we can keep a copy for
every specialization of the program. The only downside is bloating
the structure a bit, but we can tighten that up a bit if we need to.
This also lets us kill gen4_fragment_program entirely!
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Grazvydas Ignotas [Fri, 13 Jan 2017 23:10:08 +0000 (01:10 +0200)]
anv: remove some unused macros and functions
VK_ICD_WSI_PLATFORM_MAX is used, but a duplicate from wsi_common.h .
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Fri, 13 Jan 2017 17:30:13 +0000 (09:30 -0800)]
anv: Default PointSize to 1.0 if not written by the shader
The Vulkan rules for point size are a bit whacky. If you only have a
vertex shader and you use points, then you must write PointSize in your
vertex shader. If you have a geometry or tessellation shader, then it's
dependent on the shaderTessellationAndGeometryPointSize device feature.
From the Vulkan 1.0.38 specification:
"shaderTessellationAndGeometryPointSize indicates whether the
PointSize built-in decoration is available in the tessellation
control, tessellation evaluation, and geometry shader stages. If this
feature is not enabled, members decorated with the PointSize built-in
decoration must not be read from or written to and all points written
from a tessellation or geometry shader will have a size of 1.0. This
also indicates whether shader modules can declare the
TessellationPointSize capability for tessellation control and
evaluation shaders, or if the shader modules can declare the
GeometryPointSize capability for geometry shaders. An implementation
supporting this feature must also support one or both of the
tessellationShader or geometryShader features."
In other words, if the feature is disbled (the client can disable
features!) then they don't write PointSize and we provide a 1.0 default
but if the feature is enabled, they do write PointSize and we use the
one they wrote in the shader. There are at least two valid ways we can
implement this:
1) Track whether or not shaderTessellationAndGeometryPointSize is
enabled and set the 3DSTATE_SF bits based on that and what stages
are enabled, ignoring the shader source.
2) Just look at the last geometry stage VUE map and see if they wrote
PointSize and set the 3DSTATE_SF accordingly.
The second solution is the easiest and the most robust against invalid
usage of the Vulkan API, so we choose to go with that one.
This fixes all of the dEQP-VK.tessellation.primitive_discard.*point_mode
tests. The tests are also broken because they unconditionally enable
shaderTessellationAndGeometryPointSize if it's supported by the
implementation and then don't write PointSize in the evaluation shader.
However, since this is the "robust against invalid API usage" solution,
the tests happily pass. :-)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 13 Jan 2017 01:07:08 +0000 (17:07 -0800)]
anv/pipeline: Replace get_fs_input_map with get_last_vue_prog_data
This lets us delete a helper from genX_pipeline.c
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Juan A. Suarez Romero [Fri, 13 Jan 2017 16:47:57 +0000 (17:47 +0100)]
i965/vec4: Fix mapping attributes
This patch reverts
57bab6708f2bbc1ab8a3d202e9a467963596d462, which was
causing issues with ILK and earlier VS programs.
1. brw_nir.c: Revert "i965/vec4/nir: vec4 also needs to remap vs attributes"
Do not perform a remap in vec4 backend. Rather, do it later when
setup attributes
2. brw_vec4.cpp: This fixes mapping ATTRx to proper GRFn.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99391
[jordan.l.justen@intel.com: merge Juan's two patches from bugzilla]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 11 Jan 2017 23:10:48 +0000 (15:10 -0800)]
anv: Move nir_lower_wpos_center after dead variable elimination.
When multiple shader stages exist in the same SPIR-V module, we compile
all entry points and their inputs/outputs, then dead code eliminate the
ones not related to the specific entry point later.
nir_lower_wpos_center was being run prior to eliminating those random
other variables, which made it trip up, thinking it found gl_FragCoord
when it actually found something else like gl_PerVertex[3].
Fixes dEQP-VK.spirv_assembly.instruction.graphics.module.same_module.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Thu, 5 Jan 2017 10:51:38 +0000 (02:51 -0800)]
i965: Fix textureGather with RG32I/UI on Gen7.
According to the "Gather4 R32G32_FLOAT Bug" internal documentation
page, the R32G32_UINT and R32G32_SINT formats are affected by the
same bug as R32G32_FLOAT. Applying the same workarounds should be
viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt
integer data which is NaN or other sketchy floating point values.
One irritating caveat is that, because it's a FLOAT format, the
alpha channel or any set to SCS_ONE return 0x3f8 (1.0) rather than
integer 1. So we need shader code to whack those channels to 1.
Fixes GL45-CTS.texture_gather.plain-gather-int-cube-rg on Haswell.
v2: Fix swizzle component zeroing (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bas Nieuwenhuizen [Fri, 13 Jan 2017 07:55:59 +0000 (08:55 +0100)]
radv: Support loader interface version 3.
Port of
1e41d7f7b0855934744fe578ba4eae9209ee69f7:
"anv: Support loader interface version 3 (patch v2)"
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Boyan Ding [Mon, 9 Jan 2017 14:48:38 +0000 (22:48 +0800)]
mesa/get: Remove unused extra_ARB_viewport_array
Unused since
0a7691ee (mesa: Enable enums for OES_viewport_array).
Silence a warning of unused variable.
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Boyan Ding [Wed, 25 Nov 2015 05:43:06 +0000 (13:43 +0800)]
xlib: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: handle the final case in glXCreateContextAttribsARB]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Boyan Ding [Wed, 25 Nov 2015 05:27:07 +0000 (13:27 +0800)]
radeon: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
[Emil Velikov: handle the all cases]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Boyan Ding [Wed, 25 Nov 2015 05:27:06 +0000 (13:27 +0800)]
nouveau: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Boyan Ding [Wed, 25 Nov 2015 05:27:05 +0000 (13:27 +0800)]
glX_proto_send.py: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Boyan Ding [Wed, 25 Nov 2015 05:27:04 +0000 (13:27 +0800)]
loader/dri3: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Boyan Ding [Wed, 25 Nov 2015 05:27:02 +0000 (13:27 +0800)]
egl/dri2: Unify the style of function pointer calls in structs
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
[Emil Velikov: address platform_surfaceless]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Derek Foreman [Wed, 23 Nov 2016 23:01:43 +0000 (17:01 -0600)]
i915: Add XRGB8888 format to intel_screen_make_configs
This is a copy of commit
536003c11e4cb1172c540932ce3cce06f03bf44e
except for i915.
Original log for the i965 commit follows:
Some application, such as drm backend of weston, uses XRGB8888 config as
default. i965 doesn't provide this format, but before commit
65c8965d,
the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit
65c8965d makes EGL recognize format correctly so weston won't start
because it can't find XRGB8888. Add XRGB8888 format to i965 just as
other drivers do.
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Acked-by: Boyan Ding <boyan.j.ding@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Derek Foreman [Wed, 23 Nov 2016 22:40:42 +0000 (16:40 -0600)]
gbm/drm: Pick the oldest available buffer in get_back_bo
Applications may query the back buffer age to efficiently perform
partial updates. Generally the application will keep a fixed length
damage history, and use this to calculate what needs to be redrawn
based on the age of the back buffer it's about to render to.
If presented with a buffer that has an age greater than the
length of the damage history, the application will likely have
to completely repaint the buffer.
Our current buffer selection strategy is to pick the first available
buffer without considering its age. If an application frequently
manages to fit within two buffers but occasionally requires a third,
this extra buffer will almost always be old enough to fall outside
of a reasonably long damage history, and require a full repaint.
This patch changes the buffer selection behaviour to prefer the oldest
available buffer.
By selecting the oldest available buffer, the application will likely
always be able to use its damage history, at a cost of having to
perform slightly more work every frame. This is an improvement if
the cost of a full repaint is heavy, and the surface damage between
frames is relatively small.
It should be noted that since we don't currently trim our queue in
any way, an application that briefly needs a large number of buffers
will continue to receive older buffers than it would if it only ever
needed two buffers.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Jonas Ådahl [Fri, 13 Jan 2017 15:05:10 +0000 (23:05 +0800)]
egl/wayland: Avoid race conditions when on non-main thread
When EGL is used on some other thread than the thread that drives the
main wl_display queue, the Wayland EGL dri2 implementation is
vulnerable to a race condition related to display round trips and global
object advertisements.
The race that may happen is that after after a proxy is created, but
before the queue is set, events meant to be emitted via the yet to be
set queue may already have been queued on the wrong queue.
In order to make it possible to avoid this race, wayland 1.11
introduced new API that allows creating a proxy wrapper that may be used
as the factory proxy when creating new proxies via Wayland requests. The
queue of a proxy wrapper can be changed without effecting what queue
events emitted by the actual proxy will be queued on, while still
effecting what default queue proxies created from it will have.
By introducing a wl_display proxy wrapper and using this when performing
round trips (via wl_display_sync()) and retrieving the global objects (via
wl_display_get_registry()), the mentioned race condition is avoided.
Signed-off-by: Jonas Ådahl <jadahl@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Daniel Stone <daniels@collabora.com>
Jonas Ådahl [Fri, 13 Jan 2017 15:05:09 +0000 (23:05 +0800)]
egl/wayland: Cleanup private display connection when init fails
When failing to initializing the Wayland EGL driver, don't leak the
display server connection if it was us who created it.
Signed-off-by: Jonas Ådahl <jadahl@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Rhys Kidd [Fri, 13 Jan 2017 04:06:34 +0000 (23:06 -0500)]
travis: Add the new drivers etnaviv and imx
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
sguttula [Thu, 10 Nov 2016 05:59:53 +0000 (00:59 -0500)]
st/va: flush pipeline after post processing
This will flush the pipeline,which will allow to share dma-buf based
buffers.
Signed-off-by: Suresh Guttula <Suresh.Guttula@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Alejandro Piñeiro [Thu, 12 Jan 2017 18:09:17 +0000 (16:09 -0200)]
main/fbobject: throw invalid operation when get_attachment fails if needed
In most cases, if a call to get_attachment fails is because attachment
is a INVALID_ENUM. But for some specific cases, if COLOR_ATTACHMENTm
(where m >= MAX_COLOR_ATTACHMENTS) is used, it should raise an
INVALID_OPERATION exception instead.
Fixes:
GL45-CTS.direct_state_access.framebuffers_get_attachment_parameter_errors
GL45-CTS.direct_state_access.framebuffers_renderbuffer_attachment_errors
v2: extra new line before quote block. Include "color attachment" on both
new message errors (Nicolai).
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Alejandro Piñeiro [Thu, 12 Jan 2017 18:03:00 +0000 (16:03 -0200)]
main/fboject: return if it is color_attachment on get_attachment
Some callers would need that info to know if they should raise
INVALID_ENUM or INVALID_OPERATION. An alternative would be the caller
to check if the attachment is a GL_COLOR_ATTACHMENTm, but that seems
redundant as get_attachment is already doing that.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 12 Jan 2017 09:55:33 +0000 (10:55 +0100)]
mesa/main: fix version/extension checks in _mesa_ClampColor
Add a proper check for feature support, and raise an invalid enum for
GL_CLAMP_VERTEX/FRAGMENT_COLOR unconditionally in core profiles, since
those enums were explicitly removed after the extension was promoted
to core functionality (not in the profile sense) with OpenGL 3.0.
This matches the behavior of the AMD closed source driver and fixes
GL45-CTS.gtf30.GL3Tests.half_float.half_float_textures.
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Thu, 12 Jan 2017 11:23:14 +0000 (12:23 +0100)]
radeonsi: replace si_shader_context::soa by bld_base
We no longer need to use lp_build_tgsi_soa_context.
No regressions founds with full piglit run.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 11 Jan 2017 15:28:51 +0000 (16:28 +0100)]
radeonsi: replace ctx->soa.outputs by ctx->outputs
The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 11 Jan 2017 15:21:23 +0000 (16:21 +0100)]
radeonsi: move si_shader_context::soa::addr to si_shader_context
The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 11 Jan 2017 13:50:41 +0000 (14:50 +0100)]
radeonsi: allocate the array of immediates dynamically
Currently, we can store up to 256 immediates in a static array,
but this is not always enough. Instead, allocate a dynamic array
like what we currently do for temps.
This fixes a segfault with
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23
No regressions found with full piglit run.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 11 Jan 2017 01:31:24 +0000 (03:31 +0200)]
radv: remove some unused macros and functions
These seem unlikely to be used.
Also remove irrelevant comment about SKL.
v2: forgot to rebase on master
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Nanley Chery [Thu, 15 Dec 2016 02:20:26 +0000 (18:20 -0800)]
anv: Avoid some resolves for samplable HiZ buffers
v2: Simplify nested ifs (Jason Ekstrand)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 11 Jan 2017 16:12:48 +0000 (08:12 -0800)]
anv: Enable sampling from HiZ
v2: Restrict ISL_AUX_USAGE_HIZ to depth aspects
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Thu, 15 Dec 2016 17:57:48 +0000 (09:57 -0800)]
anv/blorp: Don't fast depth clear samplable HiZ buffers on BDW
Avoid the resolves that would be required if fast depth clears were
allowed for such buffers.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Tue, 10 Jan 2017 03:24:44 +0000 (19:24 -0800)]
anv: Add a helper to determine sampling with HiZ
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 5 Dec 2016 23:24:28 +0000 (15:24 -0800)]
isl/surface_state: Handle ISL_AUX_USAGE_HIZ
v2: Remove redundant x/y offset asserts (Jason Ekstrand)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 2 Jan 2017 09:06:15 +0000 (01:06 -0800)]
anv: Perform HiZ resolves only on layout transitions
This is a better mapping to the Vulkan API and improves performance in
all tested workloads.
v2: Remove unnecessary image view aspect checks (Jason Ekstrand)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 11 Jan 2017 23:12:35 +0000 (15:12 -0800)]
anv: Disable HiZ for input attachments
v2 (Jason Ekstrand):
- Add spec citation
- Drop conditional
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Tue, 6 Dec 2016 17:08:09 +0000 (09:08 -0800)]
anv: Avoid resolves incurred by fast depth clears
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 9 Jan 2017 18:44:36 +0000 (10:44 -0800)]
anv: Prepare for transitioning to the requested final layout
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 2 Jan 2017 08:44:08 +0000 (00:44 -0800)]
anv: Store depth stencil layouts
Store the current and requested depth stencil layouts so that we can
perform the appropriate HiZ resolves for a given transition while
recording a render pass.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Thu, 15 Dec 2016 01:58:41 +0000 (17:58 -0800)]
anv: Add helpers to handle depth buffer layout transitions
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 6 Jan 2017 07:34:38 +0000 (23:34 -0800)]
anv: Delete anv's HiZ op emit function
This is no longer used.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 11 Jan 2017 21:05:13 +0000 (13:05 -0800)]
anv: Use the gen8 BLORP HiZ resolving function
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 6 Jan 2017 07:32:07 +0000 (23:32 -0800)]
anv/blorp: Add a gen8 HiZ op resolve function
Add an entry point for resolving using BLORP's gen8 HiZ op function.
v2: Manually add the aux info
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Fri, 6 Jan 2017 00:46:37 +0000 (16:46 -0800)]
anv: Use gen8 BLORP HiZ clearing functions
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Wed, 11 Jan 2017 00:17:26 +0000 (16:17 -0800)]
intel/blorp_clear: Add gen8 HiZ clearing functions
Add an entry point for the optimized gen8 BLORP HiZ sequence. commit
c9eaf12de20ac4143fe79d42018bdbb5a391356f fixed a bug that was
unknowingly worked around by forcing additional clear rectangle
alignment restrictions not specified in the PRMs. Now that the bug is no
longer present, omit the additional alignment restrictions.
v2: Adjust code comment about padding
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Sun, 8 Jan 2017 02:18:43 +0000 (18:18 -0800)]
anv: Enable HiZ support for multiple subpasses
We'll be using layout transitions later on in the series which can occur
within and between subpasses. Turn this on now to simplify the change
later.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Mon, 9 Jan 2017 12:47:31 +0000 (04:47 -0800)]
anv: Use ::anv_attachment_state for toggling HiZ per subpass
We're about to enable HiZ support for multiple subpasses. Use this field
to keep track of whether or not subpass operations should treat the
depth buffer as having an auxiliary HiZ buffer.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Sat, 7 Jan 2017 23:10:57 +0000 (15:10 -0800)]
anv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ
The helper doesn't provide additional functionality over the current
infrastructure.
v2: Add comment to anv_image::aux_usage (Jason Ekstrand)
v3: Clarify comment for aux_usage (Jason Ekstrand)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Sat, 7 Jan 2017 23:47:36 +0000 (15:47 -0800)]
anv/blorp: Handle ISL_AUX_USAGE_HIZ
Prevent assert failures that would occur in the next patch.
v2: Don't remove asserts from blorp/blit (Jason Ekstrand)
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Nanley Chery [Tue, 10 Jan 2017 20:06:42 +0000 (12:06 -0800)]
intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP
We'll be switching to layout-transition based resolves which can occur
outside of a render pass. Add this sequence to BLORP, as using BLORP
will enable emitting depth stencil state outside of a render pass (among
other benefits). The depth buffer extent is ignored to enable eventual
usage in VkCmdClearAttachments().
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Emil Velikov [Fri, 16 Dec 2016 15:08:30 +0000 (15:08 +0000)]
get-typod-pick-list.sh: add new script
Typos do happen as people nominate patches for stable. This script aims
to catch most of those.
Due to the subtle nature of things, one has to pay special attention to
the output, similar to get-extra-pick-list.sh.
At the moment only the following is handled:
grep -i "CC:.*mesa-dev"
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 12 Jan 2017 22:13:21 +0000 (22:13 +0000)]
ac: automake: ensure that ./common is generated
Depending on the autoconf (or friends) version one may or may not have
the ./common folder created. Thus in the latter case we'll fail to
generate the file.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Darren Salt <devspam@moreofthesa.me.uk>
Reported-by: Darren Salt <devspam@moreofthesa.me.uk>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Ilia Mirkin [Fri, 13 Jan 2017 02:06:40 +0000 (21:06 -0500)]
nvc0/ir: only try to check for zero LOD if we aren't already forcing it
There's a levelZero flag which forces texturing to pick level zero (and
not consume an explicit LOD argument). This is set for MS targets, but
could also be set for any other incoming instruction. As that is what
determines whether a LOD argument is present, check that rather than the
more indirect isMS logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 11 Jan 2017 03:07:53 +0000 (22:07 -0500)]
nouveau: take extra push space into account for pushbuf_space calls
Ever since a long time ago when I messed around with fences, I ensure
that after a PUSH_SPACE call there is enough space to write a fence out
into the pushbuf.
However the PUSH_SPACE macro is not all-knowing, and so sometimes we
have to invoke nouveau_pushbuf_space manually with the relocs/pushes
args set. If we don't take the extra allocation from PUSH_SPACE into
account, then we will end up accidentally flushing when the code was not
expecting a flush. This can lead to various runtime and rendering
failures.
The amount of extra allocation isn't that important - it has to be at
least 8 based on the current nouveau_winsys.h setting, but even more
won't hurt. I just rounded up to powers of 2.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99354
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Grazvydas Ignotas [Sun, 8 Jan 2017 17:38:09 +0000 (19:38 +0200)]
mapi: update the asm code to support x32
Fixes crashes when both glx-tls and asm are enabled on x32.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94512
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=575458
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Nicolai Hähnle [Tue, 10 Jan 2017 14:46:17 +0000 (15:46 +0100)]
ac/nir: use ac_emit_fdiv throughout
... and eliminate emit_fdiv and nir_to_llvm_context::fpmath_md_*, which
are now unused.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 14:44:04 +0000 (15:44 +0100)]
ac/nir: use ac_build_gather_values[_extended] throughout
... and eliminate the non-ac copies. Mostly straight-forward
search & replace.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 14:39:56 +0000 (15:39 +0100)]
ac/nir: use ac_emit_llvm_intrinsic throughout
... by straight-forward search & replace, and eliminate
emit_llvm_intrinsic.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 16:20:57 +0000 (17:20 +0100)]
radeonsi: remove unused si_prepare_cube_coords
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 14:35:27 +0000 (15:35 +0100)]
amd/common: unify cube map coordinate handling between radeonsi and radv
Code is taken from a combination of radv (for the more basic functions,
to avoid gallivm dependencies) and radeonsi (for the new and improved
derivative calculations).
v2: add 0.5 offset to tex coords only after derivative calculation
v3:
- really only touch the first three coordinates
- rebase on the removal of the 1.5 --> 0.5 offset change
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 13:54:22 +0000 (14:54 +0100)]
radeonsi: only touch first three coordinates in si_prepare_cube_coords
Sourcing coords_arg[4] is actually never correct, since bias is handled
differently in tex_fetch_args anyway.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 12:16:11 +0000 (13:16 +0100)]
radeonsi: remove unused si_llvm_cube_to_2d_coords
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 10:47:22 +0000 (11:47 +0100)]
radeonsi: restrict cube map derivative computations to the correct plane
As remarked by the comment in the original code, the old algorithm fails when
(tc + deriv) points at a different cube face. Instead, simply project the
derivative directly to the plane of the selected cube face.
The new code is based on exactly differentiating (using the chain rule)
the projection onto a plane corresponding to a fixed cube map face (which
is still selected in the usual way based on the texture coordinate itself).
The computations end up fairly involved, but we do save two reciprocal
computations.
Fixes GL45-CTS.texture_cube_map_array.sampling.
v2: add 0.5 offset to tex coords only after derivative calculation
v3: go back to 1.5 offset
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Jan 2017 09:57:48 +0000 (10:57 +0100)]
radeonsi: communicate cube map coordinates more explicitly
v2: fix compile error that snuck in during rebase
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Grazvydas Ignotas [Wed, 11 Jan 2017 23:58:59 +0000 (01:58 +0200)]
ac/debug: move .gitignore for sid_tables.h too
b838f642 "ac/debug: Move sid_tables.h generation to common code." moved
sid_tables.h but forgot the corresponding .gitignore.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Thu, 12 Jan 2017 22:09:30 +0000 (14:09 -0800)]
nir/gcm: Fix a typo in a comment
Reported-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 1 Dec 2016 21:51:03 +0000 (13:51 -0800)]
nir/gcm: Rework the schedule late loop
This fixes a bug in code motion that occurred when the best block is the
same as the schedule early block. In this case, because we're checking
(lca != def->parent_instr->block) at the top of the loop, we never get to
the check for loop depth so we wouldn't move it out of the loop. This
commit reworks the loop to be a simple for loop up the dominator chain and
we place the (lca != def->parent_instr->block) check at the end of the
loop.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chuck Atkins [Fri, 6 Jan 2017 13:27:44 +0000 (08:27 -0500)]
glx: Add missing glproto dependency for gallium-xlib glx
Cc: mesa-stable@lists.freedesktop.org
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Signed-of-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 12 Jan 2017 21:54:03 +0000 (21:54 +0000)]
ac, radeonsi: automake: add missing builddir include
The generated file is correctly stored in the builddir as of earlier
commit. Yet the commit forgot to add the respective include flag thus
the compiler would error out failing to find sid_tables.h
Bugzila: https://bugs.freedesktop.org/show_bug.cgi?id=99389
Fixes: d1dc22eb466 "ac: automake: rework sid_tables.h generation"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Bas Nieuwenhuizen [Sun, 8 Jan 2017 22:23:52 +0000 (23:23 +0100)]
radv: Call NIR passes using NIR_PASS_V.
Port of
faa1edeeb7bbe9321c79587e592dce812e8caa78
"anv/pipeline: Call NIR passes using NIR_PASS_V"
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Bas Nieuwenhuizen [Sun, 8 Jan 2017 22:17:38 +0000 (23:17 +0100)]
radv: Call nir_lower_constant_initializers.
Port of
c5d664f9dc2d281c74844cef36ecb9f5862a8f6a
"anv/pipeline: Call nir_lower_constant_initializers"
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>