nouveau/codegen: allow tex offsets on non-TXF instructions (e.g. TXL)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>

nv50: only over-allocate by a page for code

The pre-fetching doesn't go too far. Tested with over-allocating by only
a page, and didn't see any errors in dmesg. Saves ~512KB of VRAM.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>

nv50: fix layerid to be the fp input number rather than vp output number

In the tests they were the same so it didn't matter, but indications are
that this is the correct behaviour. Also take this opportunity to
(trivially) support using gl_Layer in fp.

Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>

nv50: rework primid logic

Functionally identical but much simpler. Should also better integrate
with future layer/viewport changes/fixes.

Cc: 10.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Christoph Bumiller <e0425955@student.tuwien.ac.at>

glx: Pass NULL DRI drawables into the DRI driver for None GLX drawables

GLX_ARB_create_context allows making a GLX context current with None
drawable and readables, but this was never implemented correctly in GLX.
We would create a __DRIdrawable for the None GLX drawable and pass that
to the DRI driver and that would somehow work.  Now it's somehow broken.

The way this should have worked is that we pass a NULL DRI drawable
to the DRI driver when the GLX user calls glXMakeContextCurrent()
with None for drawable and readables.

https://bugs.freedesktop.org/show_bug.cgi?id=74143
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>

st/vdpau: add flush on unmap

Flush the context when we unmap a buffer, otherwise VDPAU might
start rendering the next frame while we still reference that buffer.

Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: StrangeNoises (rachel@strangenoises.org)

vdpau: flush the context before exporting the surface v2

Bugzilla (bug needs XBMC changes as well):
https://bugs.freedesktop.org/show_bug.cgi?id=73191

When VL uploads vertex buffers, it uses PIPE_TRANSFER_DONTBLOCK, which always
flushes the context in the winsys if the buffer being mapped is busy. Since
I added handling of DISCARD_RANGE, DONTBLOCK has had no effect when combined
with DISCARD_RANGE and I think the context isn't flushed anywhere else,
so no commands are submitted to the GPU until the IB is full, which takes
a lot of frames.

Using DISCARD_RANGE is not the only way to trigger this bug. The other way
is to reallocate the vertex buffer before every upload.

BTW, I'm not sure if this is the right place for flushing, but it does fix
the bug.

v2 (chk): move the flush to the right place.

Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: StrangeNoises (rachel@strangenoises.org)

glsl: Initialize ubo_binding_mask flags to zero.

Missed in commit e63bb298. Caused sporadic test failures, like
incorrect-in-layout-qualifier-repeated-prim.geom.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

gallium/radeon: fix warnings

gallium: remove PIPE_USAGE_STATIC

Reviewed-by: Brian Paul <brianp@vmware.com>

gallium: define the behavior of PIPE_USAGE_* flags properly

STATIC will be removed in the following commit.

v2: changed the definition of IMMUTABLE

Reviewed-by: Brian Paul <brianp@vmware.com>

gallium: remove PIPE_RESOURCE_FLAG_GEN_MIPS

Unused.

Reviewed-by: Brian Paul <brianp@vmware.com>

r600g,radeonsi: set resource domains in one place (v2)

v2: This doesn't change the behavior. It only moves the tiling check
    to r600_init_resource and removes the usage parameter.

Reviewed-by: Christian König <christian.koenig@amd.com>

st/mesa: fix crash when a shader uses a TBO and it's not bound

This binds a NULL sampler view in that case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74251

Cc: "10.1" "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/omx: add workaround for bug in Bellagio

Not blocking for the message thread can lead to accessing freed up memory.

Signed-off-by: Christian König <christian.koenig@amd.com>

st/omx: initial OpenMAX support v3

Featuring a full grown MPEG2 and H264 decoder and a couple of hundred bugs.

v2 (Leo): fix an error for pic_order_cnt_type 1
v3 (Leo): implement support for field decoding

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>

vl/rbsp: add H.264 RBSP implementation

Signed-off-by: Christian König <christian.koenig@amd.com>

vl/vlc: add function to limit the vlc size

Signed-off-by: Christian König <christian.koenig@amd.com>

vl/vlc: add remove bits function

Signed-off-by: Christian König <christian.koenig@amd.com>

radeon: update legal notes on UVD

Signed-off-by: Christian König <christian.koenig@amd.com>

radeon: just don't map VRAM buffers at all

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon/video: directly create buffers in the right domain

Avoid moving things around on start of stream.

Signed-off-by: Christian König <christian.koenig@amd.com>

radeon/video: seperate common video functions

Signed-off-by: Christian König <christian.koenig@amd.com>

gallium/dri2: Fix dri2_dup_image

dri2_dup_image was not copying the dri_format field.

This was causing some bugs, for example:
. we create an gbm_bo.
. we get an EGLImage from the gbm_bo.
. Bug: impossible to get again the gbm_bo from the EGLImage by
  importing. (gbm dri2 backend)

Signed-off-by: Axel Davy <axel.davy@ens.fr>

i965/vs: Fix typo in brw_compute_vue_map

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix register types in dump_instructions().

This regressed when I converted BRW_REGISTER_TYPE_* to be an abstract
type that doesn't match the hardware description.  dump_instruction()
was using reg_encoding[] from brw_disasm.c, which no longer matches
(and was incorrect for Gen8+ anyway).

This patch introduces a new function to convert the abstract enum values
into the letter suffix we expect.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

egl/glx: Remove egl_glx driver

Mesa now has a real, feature-rich EGL implementation on X11 via xcb.
Therefore I believe there is no longer a practical need for the egl_glx
driver.

Furthermore, egl_glx appears to be unmaintained.  The most recent
nontrivial commit to egl_glx was 6baa5f1 on 2011-11-25.

Tested by running weston-smoke in windowed Weston on X with i965.

Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Kristian Høgsberg <krh@bitplanet.net>

docs: update 10.1 relnotes to note GL 3.3 on r600 and radeonsi.

Signed-off-by: Dave Airlie <airlied@redhat.com>

tgsi/ureg: increase the number of immediates

ureg_program is allocated on the heap so we can just bump the
number of immediates that it can handle. It's needed for d3d10.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: make sure analysis works with large number of immediates

We need to handle a lot more immediates and in order to do that
we also switch from allocating this structure on the stack to
allocating it on the heap.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: handle huge number of immediates

We only supported up to 256 immediates, which isn't enough. We had
code which was allocating immediates as an allocated array, but it
was always used along a statically backed array for performance
reasons. This commit adds code to skip that performance optimization
and always use just the dynamically allocated immediates if the
number of them is too great.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: allow large numbers of temporaries

The number of allowed temporaries increases almost with every
iteration of an api. We used to support 128, then we started
increasing and the newer api's support 4096+. So if we notice
that the number of temporaries is larger than our statically
allocated storage would allow we just treat them as indexable
temporaries and allocate them as an array from the start.

Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/fs: Assume FBO rendering in precompile if MRT.

If multiple color outputs are written, this shader is unlikely to be
useful with a winsys framebuffer.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Guess nr_color_regions better in precompile

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

docs: Add relnotes for 10.2

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Bump version to 10.2.0-devel

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Move intel_prepare_render() above first buffer access

The driver is supposed to ensure buffers before any drawing operation, but in
do_blit_drawpixels() and do_blit_copypixels() we inspect the buffer format
before calling intel_prepare_render().  That was covered up by the
unconditional call to intel_prepare_render() in intelMakeCurrent(), but we
now only do this on the initial intelMakeCurrent call for a context
(to get the size for the initial viewport values).

https://bugs.freedesktop.org/show_bug.cgi?id=74083

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Tested-by: Alexander Monakov <amonakov@gmail.com>

st/mesa: add MESA_SHADER_COMPUTE case in shader_stage_to_ptarget()

Silences compiler warning.  Trivial.

mesa: re-wrap, fix-up comment text in formats.h

Wrap to 78 columns, fix comment formatting.
Trivial.

i965/cs: Allow ARB_compute_shader to be enabled via env var.

This will allow testing of compute shader functionality before it is
completed.

To enable ARB_compute_shader functionality in the i965 driver, set
INTEL_COMPUTE_SHADER=1.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/cs: Create the brw_compute_program struct, and the code to initialize it.

v2: Fix comment.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl/cs: Prohibit mixing of compute and non-compute shaders.

Fixes piglit test:
spec/ARB_compute_shader/linker/mix_compute_and_non_compute

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl/cs: Prohibit user-defined ins/outs in compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

main/cs: Implement query for COMPUTE_WORK_GROUP_SIZE.

v2: Improve error message.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/cs: Handle compute shader local size during linking.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

glsl/cs: Handle compute shader local_size_{x,y,z} declaration.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/cs: Implement MAX_COMPUTE_WORK_GROUP_COUNT constant.

v2: Document that the 3-element array MaxComputeWorkGroupCount is
indexed by dimension.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/cs: Implement MAX_COMPUTE_WORK_GROUP_INVOCATIONS constant.

Reviewed-by: Matt Turner <mattst88@gmail.com>
v2: Use CONTEXT_INT rather than CONTEXT_ENUM.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/cs: Implement MAX_COMPUTE_WORK_GROUP_SIZE constant.

v2: Document that the 3-element array MaxComputeWorkGroupSize is
indexed by dimension.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa/cs: Create the gl_compute_program struct, and the code to initialize it.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/cs: Handle compute shaders in _mesa_use_program().

v2: do cs after the ordered pipeline stages for consistency.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl/cs: update main.cpp to use the ".comp" extension for compute shaders.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl/cs: Populate default values for ctx->Const.Program[MESA_SHADER_COMPUTE].

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/cs: Add a MESA_SHADER_COMPUTE stage and update switch statements.

This patch adds MESA_SHADER_COMPUTE to the gl_shader_stage enum.
Also, where it is trivial to do so, it adds a compute shader case to
switch statements that switch based on the type of shader.  This
avoids "unhandled switch case" compiler warnings.

Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl/cs: Change some linker loops to use MESA_SHADER_FRAGMENT as a bound.

Linker loops that iterate through all the stages in the pipeline need
to use MESA_SHADER_FRAGMENT as a bound, so that we can add an
additional MESA_SHADER_COMPUTE stage, without it being erroneously
included in the pipeline.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/cs: Add dispatch API stubs for ARB_compute_shader.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa/cs: Add extension enable flags for ARB_compute_shader.

Reviewed-by: Matt Turner <mattst88@gmail.com>

gallivm: fix F2U opcode

Previously, we were really doing F2I. And also move it to generic section.
(Note that for llvmpipe the code generated is definitely bad, due to lack
of unsigned conversions with sse. I think though what llvm does (using scalar
conversions to 64bit signed either with x87 fpu (32bit) or sse (64bit)
including lots of domain changes is quite suboptimal, could do something like
is_large = arg >= 2^31
half_arg = 0.5 * arg
small_c = fptoint(arg)
large_c = fptoint(half_arg) << 1
res = select(is_large, large_c, small_c)
which should be much less instructions but that's something llvm should do
itself.)

This fixes piglit fs/vs-float-uint-conversion.shader_test (maybe more, needs
GL 3.0 version override to run.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>

tools/trace: Handle index buffer overflow gracefully.

Trivial.

docs/GL3.txt: update r600 status

This updates the r600 driver status to 3.3 being fully supported.

Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g: add support for geom shaders to r600/r700 chipsets (v2)

This is my first attempt at enabling r600/r700 geometry shaders,
the basic tests pass on both my rv770 and my rv635,

It requires this kernel patch:
http://www.spinics.net/lists/dri-devel/msg52745.html

v2: address Alex comments.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: enable GLSL 3.30 on evergreen GPUs

This throws the switch to enable GL 3.3 and GLSL 330.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: properly propogate clip dist write value

This moves the value from the GS shader to the copy shader so the registers
are setup correctly.

fixes tests/spec/glsl-1.50/execution/geometry/clip-distance-out-values.shader_test

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: calculate a better value for array_size (v2)

attempt to calculate a better value for array size to avoid breaking apps.

v2: use 0xfff like streamout, suggested by Grigori

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: fix CAYMAN geometry shader support

cayman has a different end of program bit, so do that properly.

fixes hangs with geom shader tests on cayman.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: fix up shader out misc stuff for copy shader

set the correct values so the misc out register is setup correctly
for the copy shader.

This also updates the state for the gs copy shader so the hw
gets programmed correctly.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: port the layered surface rendering patch from radeonsi

This just makes r600 and evergreen do what the radeonsi codepaths do
for layered rendering. This makes the 2d amd_vertex_shader_layer test
pass on evergreen.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: initial VS output layer support

This just adds support for emitting the proper value in the VS out misc.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: setup const texture buffers for geom shaders

This just enables the workarounds we have for vertex/pixel shaders
for geom shaders as well.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: calculate correct cut value

This selects the cut value depending on the shader selected.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: fix dynamic_input_array_index.shader_test

This follows what fglrx does, it unpacks the input we are
going to indirect into a bunch of registers and indirects
inside them.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: add support for indirect geom ring writes

We need to be able to write to the ring using a base register
for when we emit vertices in a loop, in theory the SB compiler
could collapse these indirect writes to direct writes if the
register value is constant and known, but that is outside my
pay grade.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: write proper output prim type

Vadim's code derived it from the info.mode, but it needs
to be takes from the geometry shader output primitive.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: enable instance cnt register with new enough kernel

The instance cnt register was missing for a few kernels,
with a new enough kernel we can output it.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: add primitive input support for gs

only enable prim id if gs uses it

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: emit streamout from dma copy shader

This enables streamout with GS in the mix, from the
VS dma shader.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g/gs: fix cases where number of gs inputs != number of gs outputs

this fixes a bunch of the geom shader built-in tests

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: increase array base for exported parameters

Trivial fix to Vadim's code.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: initialise the geom shader loop registers.

As we do for vertex and pixel shaders.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: emit NOPs at end of shaders in more cases

If the shader has no CF clauses at all emit an nop
If the last instruction is an ENDLOOP add a NOP for the LOOP to go to
if the last instruction is CALL_FS add a NOP

These fix a bunch of hangs in the geometry shader tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: don't enable SB for geom shaders

SB needs fixes for three GS instructions it seems to raise
them outside loops etc despite my best efforts.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g/sb: add MEM_RING support

Although we don't use SB on geom shaders, the VS copy shader will use it
so we might as well implement MEM_RING support in sb.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: don't fail if we can't map VS->GS ring entries

This can happen in normal operation, so don't report an error on it,
just continue.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: initial support for geometry shaders on evergreen (v2)

This is Vadim's initial work with a few regression fixes squashed in.

v2: (airlied)
fix regression in glsl-max-varyings - need to use vs and ps_dirty
fix regression in shader exports from rebasing.
whitespace fixing.
v2.1: squash fix assert

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: add hw register definitions for GS block setup

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: defer shader variant selection and depending state updates

[airlied: fix dropped streamout line - fix for master]

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g/bc: add support for indexed memory writes.

It looks like we need these for geom shaders in the future.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

r600g: move barrier and end_of_program bits from output to cf struct (v2)

v2: fix regression on r600 NOP instructions.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g: split streamout emit code into a separate function

For geometry shaders we need to call this code from a second place.

Just move it out for now to keep future patches cleaner.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

r600g,radeonsi: skip unnecessary buffer_is_busy call, add a comment

r600g,radeonsi: skip busy-checking for DISCARD_RANGE if it has been done already

r600g,radeonsi: treat DYNAMIC and STREAM usage as STAGING

gallium: remove PIPE_CAP_MAX_COMBINED_SAMPLERS

This can be derived from the shader caps.

All GPUs from ATI/AMD, NVIDIA, and INTEL have separate texture slots
for each shader stage.

mesa: remove stray bits of GL_EXT_cull_vertex

GL_EXT_cull_vertex was removed back in 2010 in commit 02984e3536
but these bits still lingered.

Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Fix continue statements in do-while loops.

From the GLSL 4.40 spec, section 6.4 (Jumps):

    The continue jump is used only in loops. It skips the remainder of
    the body of the inner most loop of which it is inside. For while
    and do-while loops, this jump is to the next evaluation of the
    loop condition-expression from which the loop continues as
    previously defined.

Previously, we incorrectly treated a "continue" statement as jumping
to the top of a do-while loop.

This patch fixes the problem by replicating the loop condition when
converting the "continue" statement to IR.  (We already do a similar
thing in "for" loops, to ensure that "continue" causes the loop
expression to be executed).

Fixes piglit tests:
- glsl-fs-continue-inside-do-while.shader_test
- glsl-vs-continue-inside-do-while.shader_test
- glsl-fs-continue-in-switch-in-do-while.shader_test
- glsl-vs-continue-in-switch-in-do-while.shader_test

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Make condition_to_hir() callable from outside ast_iteration_statement.

In addition to making it public, we also need to change its first
argument from an ir_loop * to an exec_list *, so that it can be used
to insert the condition anywhere in the IR (rather than just in the
body of the loop).

This will be necessary in order to make continue statements work
properly in do-while loops.

Cc: mesa-stable@lists.freedesktop.org
Acked-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/blorp: do not use unnecessary hw-blending support

This is really not needed as blorp blit programs already sample
XRGB normally and get alpha channel set to 1.0 automatically by
the sampler engine. This is simply copied directly to the payload
of the render target write message and hence there is no need for
any additional blending support from the pixel processing pipeline.

The blending formula is anyway broken for color components, it
multiplies the color component with itself (blend factor is the
component itself).
Alpha blending in turn would not fix the alpha to one independent
of the source but simply used the source alpha as is instead
(1.0 * src_alpha + 0.0 * dst_alpha).

Quoting Eric:

 "If we want to actually make the no-alpha-bits-present thing work,
  we need to override the bits in the surface state or in the
  generated code.  In the normal draw path, it's done for sampling
  by the swizzling code in brw_wm_surface_state.c, and the blending
  overrides is just to fix up the alpha blending stage which
  doesn't pay attention to that for the destination surface."

If one modifies piglit test gl-3.2-layered-rendering-blit to use
color component values other than zero or one, this change will
kick in on IVB. No regressions on IVB.

This is effectively revert of c0554141a9b831b4e614747104dcbbe0fe489b9d:

    i965/blorp: Support overriding destination alpha to 1.0.

    Currently, Blorp requires the source and destination formats to be
    equal.  However, we'd really like to be able to blit between XRGB and
    ARGB formats; our BLT engine paths have supported this for a long time.

    For ARGB -> XRGB, nothing needs to occur: the missing alpha is already
    interpreted as 1.0.  For XRGB -> ARGB, we need to smash the alpha
    channel to 1.0 when writing the destination colors.  This is fairly
    straightforward with blending.

    For now, this code is never used, as the source and destination formats
    still must be equal.  The next patch will relax that restriction.

    NOTE: This is a candidate for the 9.1 branch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

radeon/uvd: fix feedback buffer handling v2

Without the correct feedback buffer size UVD runs
into an error on each frame, reducing the maximum FPS.

v2: fixing Michels comments

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: "10.1" "10.0" "9.2" <mesa-stable@lists.freedesktop.org>

i965: Use brw_bo_map[_gtt]() in intel_miptree_map_raw().

This moves the intel_batchbuffer_flush before the drm_intel_bo_busy
call, which is a change in behavior.  However, the old behavior was
broken.

In the future, we may want to only flush in the batchbuffer references
the BO being mapped.  That's certainly more typical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Use brw_bo_map() in intel_texsubimage_tiled_memcpy().

This additionally measures the time stalled, while also simplifying the
code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Eric Anholt <eric@anholt.net>